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PCB007-Aug2018

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38 PCB007 MAGAZINE I AUGUST 2018 tion. He concluded with a summary of the key "Global Strategy" for success. The second presenta- tion was by J.R. Strick- land and Jerry Magera of Motorola Solutions: "How MSI Applied Technology Beat the Microvia Hidden Threat." This was a sum- mary and report on their research into stacked-mi- crovia failures that were escaping into products. This report was the main substance of the recently released IPC White Paper, IPC-WP-023 "IPC Technol- ogy Solutions White Paper on Performance-Based Printed Board OEM Ac- ceptance—Via Chain Continuity Reflow Test: The Hidden Reliability Threat—Weak Microvia Interface." Starting in 2010, stacked microvias begin ex- hibiting field failures and steps were taken to understand why. The product failures were in- termittent in nature but more often at hot tem- peratures. This led to their unpredictable reli- ability. Existing quality controls and reliabili- ty testing was not showing up these defects. Various experiments were conducted to find a fool-proof method of quality control. By 2011, an in-situ reflow test of six passes through the SMT reflow oven while instrumented with a 4-wire Kelvin resistance circuit was finalized and contained the problem. The problem was a weak microvia interface to the prior plated copper on stacked vias. Communication and consulting with industry colleges indicated they were having similar problems. All new microvia designs were to use staggered mi- crovia chains until the root cause was thoroughly un- derstood. A board coupon was estab- lished of the mi- crovia chain and this proved to be effective to screen each board before assembly. IPC TM- 650 2.6.27A was released in September 2017 as a standard for this Pb-free reflow oven ac- ceptance test. MSI has had zero product fail- ures since implementation. The reflow coupon consists of six daisy chains to test each board: • S1 chain of staggered microvias • SX2 chain of stacked microvias • S3 smallest finished hole size PTH via • S4 & S5 daisy chain of constructed of via features used in the corresponding PWB • S6 FHS of greatest number of PTH, PIH component via They concluded with promises to share their data as they search for the root cause of this microvia problem, as stacked microvias are in- evitable in future high-reliability designs. Ad- ditional work is needed by industry to identify root cause and implement corrective actions. The third presentation, "HDI Microvia Reliability for any Temperature Ex- treme," was presented by Kevin Knadle of I3 Elec- tronics. Kevin, formerly of IBM, gave an excellent history of PTH reliability testing at IBM and the use of current induced thermal cycle (CITC) testing. Covered as IPC- TM-650 2.6.26 Method B, this small, single-net coupon of 100 vias is only 1.75" x 0.3" and de- signed by IBM to be used many times on a pan- el and easily adapted to in-line process moni- toring. The test uses current to heat the cou- pon at three degrees per second to 245°C for a dwell time of 40 seconds and repeats the cycle for 200-700 cycles per day. The temperature co- efficient of resistance (TCR) is measured con- tinuously and used to determine the coupon's temperature. A 4-wire resistance bridge moni- tors the via daisy chain. The CITC cycles were verified by FEA mod- eling, TMA, and Moiré and has been used by IBM for 25 years. The rapid nature of the test and the small size of the coupons has lead IBM and I3 to be able to characterize many impor- Kevin Knadle Jerry Magera J.R. Strickland

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