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12 DESIGN007 MAGAZINE I AUGUST 2018 assembly. For example, about four years ago we did a project that had a wafer-to-wafer con- nection. We used a nano silver technology to join a CMOS pre-amplifier chip directly to an indium phosphide avalanche photo diode. We were connecting those two chips to each other, and we were doing it on a 32-micron pitch with 6-micron pillars. Today, they're down to about 22-micron pitch, and the goal is to get it to 15-micron pitch. IBM Zurich has been very active in using nano copper as the bonding medium to assemble fine-pitch packages down to about 40-micron pitch onto printed circuit boards. I think that there will necessarily be materials development that will allow us to achieve those finer pitches. How fine a pitch we have to go to is a different ques- tion. As we go to too fine a pitch, what hap- pens to the printed cir- cuit board? I do think that, especially in the kinds of products that are going to use these super fine pitch devices, you're starting to see a trend toward more and more flex and flex rigid type structures. The one area where t h o s e p a c ka g e s a re going to be a big player is in areas such as IoT. No other markets are big enough to justify processing of devices at a panel level like that, because most of the tech- nologies that we use, and most of the designs that we use, just don't use enough volume to justify putting together a panel processing line, when you look at the capacity. We have to look at the market side of things as well—not just at the technology. I think what you'll find is that wafer-level packaging will continue toward finer pitches, but as the wafer-level packaging ties to technology, it is going to be for very specific applications, where the volume justifies it. In those cases, they'll use a specialized substrate. With the general print circuit board market, obviously it is still going to have to advance, but the general cir- cuit board market will continue, at least for the next decade or so, to be driven by leading-edge packages that are essentially trying to integrate multiple devices into a single package that can then be surface-mounted onto a circuit board. Things like the video cameras for cell phones, for example, are classic 3D packages. They continue to evolve, although not very rapidly, because the solution seems to work pretty well. I'm not saying that there won't be millions of wafer-level packages mounted on printed circuit boards. But basically, wafer- level packaging serves a niche market, admit- tedly a very large niche market, but I think the niche market has pri- marily been IoT and to a certain level the cell- phone market. Holden: There's always more and more inte- gration of silicon, and I believe that the sys- tem-in-package, SiP, is a bigger trend. As that trend moves on, you can reduce the num- ber of flex circuits and things like that into a simpler construction. Bauer: Yes, I hear you. The real battle is going to be between what is more efficient, and not necessarily from a tech- nical perspective, from the chip side, but more from a cost/performance analysis between sys- tem-in-package and further integration at the chip level. Obviously, Intel took the micropro- cessor forward a long way and integrated the video processor and that sort of thing into it. Everybody rang the death knell of the video processor, and yet today's top-end computers still have a separate video processor. Figure 1: Texas Instruments wafer-level 155-pin WCSP, fully integrated power management with power path and battery charger. Image source: © Raimond Spekking, Wikimedia Commons

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