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32 DESIGN007 MAGAZINE I AUGUST 2018 The design environment can allow the user to assign, group, plan, and connect the vari- ous interfaces of the system. Data buses can be represented and treated as one path entity, and once the route has been planned, the user can manipulate the routing escape breakout and channels and modify the escape sequencing and assignment to create the interconnect in as few layers as possible, possibly in one (Figure 3). The system designer can also use this capa- bility to look at various versions of partitioning and organization—should the CPU connect to the memory on the PCB, or should the con- nectivity be integrated into the package or an interposer (Figure 4)? With 2.5 and 3D integration in the package, system planners now have additional integra- tion vehicles available to help save space and meet high-speed signal bus constraints. Those designs that require a CPU working with a high- density memory like high-bandwidth memory (HBM) can take advantage of the close proxim- ity and tighter integration that can be achieved in an IC package or an interposer rather than a PCB. Advanced packaging technologies are now one more vehicle allowing the system designer to implement in a smaller form fac- tor; having a cross-domain system planning tool that can manage the design in the PCB and packaging space is an advantage. Once the overall design is planned at a high level of abstraction, the system design can then be transferred over to the implementation tools. Depending on the design's complexity, it may spawn one or many databases including not only the PCB design, but also the package design, possibly an interposer, or the design of the integrated circuit itself. The system design team moves from a higher level of abstrac- tion to the more detailed substrate and board implementations. Here, the detailed routing and manufacturing constraints can be applied, and a more precise level of co-design can be leveraged. Co-Design The updates and engineering change orders (ECOs) in the design certainly do not stop at the initial planning phase. The ability to con- tinue to make changes and updates as the design implementation is completed is a nec- essary capability as implementation and more detailed analysis exposes additional issues. In the implementation phase, the PCB designer must focus on escape routing, work- ing within the maximum layer count while also meeting the signal and power integrity requirements of the design. At this stage, we are applying very specific routing technologies to meet the signal integrity and power integrity requirements of the system. The PCB designer may have no option other than to work with the packaging engineer to swap assignments or optimize the interconnect to meet these goals. This concept of co-design is not new or unique. For years, designers have been using various techniques to plan and co-design between IC packages and the PCB. Spread- sheets are often used to define and manage footprints in the design. However, even a Figure 4: Hierarchy options.

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