62 DESIGN007 MAGAZINE I AUGUST 2018
a trace width of .0045", intra-pair spacing of
.008", and substrate thickness of .005" between
trace and upper/lower reference plane, to
achieve characteristic impedance of 91.2 ohms.
Meanwhile, model 4B has the same parameter
setting as 4A, except the substrate thickness
between the trace and upper/lower reference
plane is increased to .007", to achieve charac-
teristic impedance of 103.2 ohms (i.e., within
±10% tolerance of the nominal 100 ohms).
By field solving the four-port simulation
topology depicted in Figure 3 and differen-
tial mode conversion, far-end crosstalk of the
transmission line models in Table 2 are plot-
ted in Figure 4 (i.e., from 1MHz to 30GHz).
Across the wideband up to 30GHz, crosstalk
for model 3A is about 3dB lower versus 3B.
Similarly, crosstalk for model 4A is at least
2.5dB lower versus 4B. This result indicates
that for both microstrip and
stripline in differential mode,
thinner substrate or dielec-
tric between a PCB trace and
an adjacent reference plane
reduces the signal crosstalk.
Summary
The study presented here
proves that crosstalk can be
minimized by reducing the
dielectric thickness between
a PCB trace and the adjacent
reference plane. This simple
implementation serves as
an additional way to further reduce uninten-
tional coupling, alongside other good PCB lay-
out practices such as increasing the coupled
distance and decreasing the coupled length
between adjacent transmission lines.
DESIGN007
References
1. Barry Olney, Beyond Design, Signal Integ-
rity, Part 2, November 2014.
2. Altera, High-Speed Board Layout Guide-
lines.
Chang Fei Yee is a hardware engineer
with Keysight Technologies. His respon-
sibilities include embedded system
hardware development, and signal and
power integrity analysis.
Figure 4: Simulated plots of far-end crosstalk for transmission line models
listed in Table 2.
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