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Design007-Aug2018

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64 DESIGN007 MAGAZINE I AUGUST 2018 Article by Yuriy Shlepnev SIMBERIAN INC. The usual way of signaling through PCB interconnects is a two-level pulse, an encoding of 1s and 0s or bits, named NRZ (non-return- to-zero) or PAM-2 line code type. Increasing the data rate with the NRZ code type presents some obstacles. For a 28 Gbps NRZ signal, the bit time is about 35.7 ps with the main spectral lobe below 28 GHz. For a 56 Gbps NRZ signal, the bit time is about 17.86 ps, with the main spectral lobe below 56 GHz. One can feel the problem already: Getting PCB interconnect analysis and measurements up to 56 GHz and beyond is very challeng- ing, to say the least. In addition, the expected attenuation (dielectric, conductor and rough- ness losses) would also be an obstacle for 56 GHz NRZ. To reduce the bandwidth of the sig- nal, pulse amplitude modulation with four lev- els (PAM-4) is being used more frequently on production boards. Instead of single bits, symbols 00, 01, 10, and 11 are coded by four levels of the pulse and the symbol time is twice as large as the bit time for NRZ signal with the same data rate; that is about 35.7 ps for 56 Gbps PAM-4—the same as for 28 Gbps NRZ! If we know how to design interconnects that correlate with the measurements for 28 Gbps NRZ, is it going to be a free lunch to move to 56 Gbps NRZ? It's not so easy, as I learned from Alex Manukovsky's tutorial, "A step by step guide for channel modeling and simula- tion that correlate to lab measurement for 25 Gb NRZ & 56 Gb PAM-4 applica- tions" and the panel discussion, "The Case of the Closing Eyes: Is PAM the Answer? Is NRZ dead?" at DesignCon 2018. So, to look into this problem, I decided to do a numerical experiment and compare the pre- dictability of the interconnects for NRZ and PAM-4 signals of the test board EvR-1 featured in our DesignCon 2018 paper "40 GHz PCB Interconnect Validation: Expectations vs. Real- ity," co-written with Marko Marin of Infinera. We used the "sink or swim" formula for predictable interconnect design. It is based on three components: interconnect geometry adjustments + identified material models + validated software -> predictable intercon- nects. With all three components in place, we were able to reliably predict behavior of most of the interconnect structures on the EvR-1 board without additional tuning or calibration for the 28-30 Gbps NRZ signal. For instance, Figure 1 depicts a simple dif- ferential link with two segments of 1.1" Moving From 28 Gbps NRZ to 56 Gbps PAM-4: Is it a Free Lunch? Figure 1: A simple differential link shows how to reliably predict behavior.

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