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PCB007-Sept2018

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14 PCB007 MAGAZINE I SEPTEMBER 2018 SAP and mSAP are processes commonly used in IC substrate fabrication. As this tech- nology is adapted to and integrated into PCB manufacturing it has the potential to fill a gap between IC fabrication and PCB fabrication ca- pabilities. Subtractive etch PCB fabrication has a limiting factor of finer line/space capability and IC fabrication is limited by a small overall panel size. As these processes are adapted to PCB manufacturing, there is the opportunity to fabricate on larger panel sizes with sub-25-mi- cron trace and space. In PCB manufacturing, both SAP and mSAP processing start with the core dielectric and a thin layer of copper. A common differentiation between the two processes is the thickness of the seed copper layer. Generally, SAP process- ing begins with a thin electroless copper coat- ing (less than 1.5 mm) and mSAP begins with a thin laminated copper foil (greater than 1.5 mm). There are multiple ways to approach this technology and decisions can be based on vol- ume requirements, costs, capital investment needed and process knowledge. The Process Both the SAP and mSAP, follow a similar process. First, a thin layer of copper is coated on the substrate. This is followed by a negative pattern design. Copper is then electroplated to the desired thickness and the seed copper lay- er is removed. For insight into additive PCB processing steps, I spoke with Mike Vinson, president and CTO of Averatek, a California-based company specializing in a catalytic ink that enables ad- ditive processing. He shared information and insight into technology based on Averatek's IP. Averatek's Atomic Layer Deposition (ALD) precursor ink can be utilized for both low-vol- ume and high-volume applications and fully additive or semi-additive processes. The cat- alytic ink controls the horizontal dimensions of the line width and spacing. The vertical di- mension of the metal thickness is controlled by an additive process that deposits metal only on the patterns defined by the photoresist. Averatek's process consists of six basic steps: 1. Drill vias in the substrate using either mechanical or laser drills. (Note: This step is optional if the customer's process includes creating vias after the Averatek process has been completed or does not include vias. 2. The substrate is then prepared for processing. In most cases, this is a simple cleaning and mounting of the material in the appropriate material handling system. 3. Coat and cure the substrate with the Averatek ALD precursor catalytic ink, resulting in a sub-nano-layer (<1 nm thick) of catalytic material. 4. Deposit electroless copper on the precursor. The copper thickness ranges from 0.1 µm to 1.0 µm. 5. Image a layer of photoresist using photo- lithographic techniques to create the patterns where copper will be deposit- ed. The geometry of lines and spaces that can be produced at this point is anything above 5 µm. 6. Electrolytic copper plating will finish out the circuits, followed by stripping the remainder of the resist and flash etching. This technology enables very fine lines on flexible or rigid substrates, among other mate- rials, at a very competitive cost. Since the holes are plated along with the traces, a smooth and seamless transition can be made. Many of the applications requiring fine-line geometries sup- port high-speed and therefore high-frequency signals, the smoothness and quality of the con- ducting metal is critical. The process described above produces conductors whose cross-sec- tions are rounded and whose surfaces are In PCB manufacturing, both SAP and mSAP processing start with the core dielectric and a thin layer of copper.

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