Issue link: https://iconnect007.uberflip.com/i/1024460
56 PCB007 MAGAZINE I SEPTEMBER 2018 Article by E. Walch, DJ., C. Rietmann, Ph.D., and A. Angstenberger, Ph.D. MACDERMID ENTHONE ELECTRONIC SOLUTIONS Abstract The industry is seeing ever-more stringent requirements of interconnect technologies (ICT) from die through final assembly, in par- ticular digital and analog high frequencies, un- distorted signal propagation and efficient heat propagation are concerned. From wafer level packaging to the finished printed circuit board, copper pillars, and solid copper posts (with printed circuitry it is copper filled through-ho- les, respectively) continue to play a vital role in coping with high-speed/high-frequency and high wattage of sub and final assemblies. Commonly used packaging concepts com- prising wafer level plating, through-silicon-vi- as (TSV), redistribution layer design (RDL), in- termediate pillars, macrobumps and copper-fil- led through-holes in the final circuitry will be addr essed in this article, followed by an over- look of the extremely different pillar geometries within each pack aging level, posing individual challenges on the copper plating chemistry and process. Practical aspects, namely dialing in the chemistry additives and process windows to match the relevant applications' needs will be reported, as well as the ongoing R&D work tar - geted for current and future requirements. The article concludes with actual research results on achievable copper textures and the subse - quent performance of the plated copper inter- connects as far as crystal lattices and the rela- ted thermal reliability are concerned. Introduction Chasing the Speed–Coping with Heat Stunning die architectures and thus the ubi- quitous subsequent miniaturization throug- hout any overall electronic assembly continue to gather momentum on the basic current and future challenges on interconnect technology (ICT) namely: • Signal (analog and digital) frequencies up to 100 GHz, even beyond • Heat generation up to 150 W/cm 2 • Utilization of 3D structures (component stacks)