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NOVEMBER 2018 I DESIGN007 MAGAZINE 43 Figure 4 shows the topology of a typical PDN, which includes the voltage regulator module (VRM), bulk bypass and decoupling capaci- tors, plane, die capacitance, BGA via, and via spreading inductance. Each of these compo- nents has a specific resonant frequency where the impedance will be low. However, these components interact to create anti-resonance peaks that may occur at undesirable frequen- cies and wreak havoc on an otherwise stable supply. The target impedance (Ztarget) of the PDN is the combination of the worst-case transient current and the voltage noise specification, which act together to set the maximum allow - able PDN impedance with an assured perfor- mance. Target impedance is the most crucial metric when evaluating PDN performance. The further the PDN impedance is above the target impedance, the greater the risk of inter- mittent operation or even complete product failure. Taking the VRM and planes into consider- ation, selected values of bypass and decoupling capacitors are added to the PDN to lower the impedance at a particular frequency (Figure 5). Capacitors reach their minimum impedance at their resonant frequency, which is deter- mined by the capacitance, equivalent series resistance (ESR), and the equivalent series inductance (ESL) together with the mount- ing inductance. To meet the target impedance at a particular frequency, a capacitance value is chosen so that when mounted on the PCB, it will resonate at the desired frequency and have an impedance that is equal to its ESR. Then, a sufficient num- ber of those capacitors are placed in par- allel so that the combined parallel ESRs approach the desired target impedance. As one can see from Figure 6, each value capacitor has a different resonant frequency depression. Thus, one would assume that by placing many different values of capacitors on the board, the entire frequency range would be covered or have minimal impedance from DC to maximum frequency. Unfortunately, it is not as simple as that. Decoupling capacitors are only effective up to about 200 MHz; above that, only on-die capacitance or planar capacitance can reduce the PDN impedance significantly. In Figure 6, I used a thin core dielectric of 2.3 mils between the planes to lower the effective impedance at high frequency. This is relatively easy to accomplish with multiple plane layers in the stackup—another bonus! This strategy pro- vides low impedance up to 1.58 GHz, in this case. Providing a balance of capacitors selected at the right frequencies and combined with pla- nar capacitance can lower the anti-resonance peaks to the target impedance up to the maxi- mum operating frequency. Key Points: • The power and ground planes in a high- speed, multilayer PCB perform six crucial functions • The high number of power supplies gener- ally leads to higher layer count substrates • These days, the majority of stackup layers of a complex design are reserved for power distribution • Power planes can be split into many dif- ferent power areas, but digital circuits are normally referenced to the same ground, so there is no real need to split a ground plane Figure 5: Target impedance, VRM, capacitor, and plane profiles of a PDN.