Issue link: https://iconnect007.uberflip.com/i/1108006
12 FLEX007 MAGAZINE I APRIL 2019 some of the challenges we faced and the steps we took to overcome them. Note: no tarantulas were harmed during the writing of this article or in the design of any circuits. 1. Bend Radius Recommendations— You're Joking, Right? The bend radius recommendations from IPC- 2223 (Table 1) provide a valiant starting place. But, increasingly, we are so far from these guidelines that design teams ask if we're joking when we suggest them. It is now more com- mon than not for us to exceed them, and over time, we have learned to accommodate much tighter bends than what IPC recommends. But there have been painful lessons along the way; these recommendations exist for a reason. Figure 1 illustrates one particularly cringe- worthy example. This is a 3-layer circuit (for simplicity, only Layer 2 is shown in the graphic) that is reduced to two layers in the bend regions. The conductors in the bend region were crack- ing at high rates during assembly. In hindsight, the design mistakes are glaring: • The tight bend radii are uncontrolled: The two bends are respectively 1.0x and 1.5x the circuit thickness or about 10 times tighter than IPC guidelines. These are effectively creases. It is possible to crease 2-layer flexes, but the creasing operation must be well-controlled and only occur one time—creased circuits must never be reopened. Such care was not taken during this assembly process • The bends begin right at the stiffened region: This is not recommended because it concentrates stress on the conductors. Ideally, there should be 0.5–1.0 mm of length after the stiffened region before a bend • Solder mask in the bend region: The sol- der mask (3) extends beyond the stiffener (1) and into the flex region to accommo- date a trace on Layer 1 (not shown in this graphic). Solder mask should always be supported by a stiffener with at least a Table 1: Bend radius recommendations from IPC-2223 Sectional Design Standard for Flexible/Rigid-Flexible Printed Circuits. Figure 1: Design renderings of a recent FPC failure due to cracked traces, including a 3D illustration of the tight bends (L), and a snapshot of the Layer 2 routing (R), showing some of the features that contributed to the failure.