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Design007-June2019

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80 DESIGN007 MAGAZINE I JUNE 2019 The PCB stackup shown in Figure 2 is applied to this 3D model, where solid planes exist on layer 2 and 3. All the four copper layers are 1.2 mils thick and FR-4 m aterial is used as the PCB substrate. The two signal traces are 15 mils apart, which is triple the signal trace width for minimum crosstalk due to forward current propagation. A stitching via is placed 20 mils off each signal via, connected to the reference plane on layer 2 and extending to layer 4. However, voids are placed on the layer 3 reference plane to break the electrical connectivity between the planes on layer 2 and 3. This simulates the effect of RPD on signal crosstalk by switching the refer- ence from ground to power or vice versa after the signal layer transition through the via. From a crosstalk perspective, port 1 and port 2 terminations refer to the transmitting and receiving ends, respectively, of the aggressor line. On the other hand, port 3 and port 4 ter- minations refer to the transmitting and receiv- ing ends, respectively, of the victim line. In model 1B (Figure 3), a stitching capaci- tor is inserted into the void on the right side (i.e., highlighted in red) to electrically connect the reference plane on layer 3 and the stitch- ing via extending from the reference plane on layer 2. Th rest of the portion is the same as model 1A. This ideal 0.1uF capacitor, without parasitic resistance (ESR) and parasitic induc- tance (ESL) [2] serves as a single return path in transmission line. On the other hand, in model 1C depicted in Figure 4, one more ideal 0.1uF stitching capac- itor is inserted into the void on the left side, highlighted in red, to electrically connect the Figure 1: 3DEM structure in model 1A. Figure 4: The 3DEM structure in model 1C. Figure 3: The 3DEM structure in model 1B. Figure 2: The PCB stackup discussed here.

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