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82 DESIGN007 MAGAZINE I JUNE 2019 for model 1A, 1B and 1C is 50mVpp, 45mVpp and 30mVpp respectively. The smallest amplitude of noise is induced at far-end point of victim line in model 1C due to the least crosstalk incurred, contributed by more return paths provided by the addition- al stitching capacitor, versus the single return path with only one stitching capacitor in mod- el 1B and total RPD (i.e., without a stitching capacitor) in model 1A. The study is further carried out to analyze the effect of ESR and ESL on mitigating the crosstalk due to RPD. Practically, a discrete ca- pacitor has intrinsic parasitic ESR and ESL in series with it, depicted in Figure 7. The 3DEM simulation is repeated on model 1C, but vary- ing the value of ESR and ESL in the two stitch- ing capacitors respectively. With reference to S41 plots in Figure 8, ESR of 0.15ohm wors- ens the FEXT by 0.075dB at a frequency near 500MHz. Similarly, with reference to S41 plots in Figure 9, ESL of 0.5nH intensifies the FEXT by 1.5dB at frequency near 500MHz. A further increase of ESL to 2nH contributes an addition- al 0.4dB to FEXT. In fact, the ESR and ESL are directly propor- tional to the impedance of the stitching capac- itor. A larger impedance in the stitching ca- Figure 9: S41 plots for model 1C with effect of ESL at full frequency span (left) versus zoomed in (right). Figure 8: S41 plots for model 1C with effect of ESR at full frequency span (left) versus zoomed in (right). Figure 7: Simplified model of practical capacitor with ESR and ESL.

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