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76 DESIGN007 MAGAZINE I JULY 2019 and dozens of passive devices. The largest component is the microprocessor chip. Figure 1 shows the footprint for the microprocessor chip. It is an LGA package with 8X8 array and 64 I/Os. The pad size is 250 µm and the pitch is 400 µm, which leaves the space between pads at 150 µm. One of the biggest challenges is how to es- cape route the traces under this processor chip. Different options were considered for the escape routing. The initial proposal from the designer was to have a 1:1 conversion. The original rigid board is a six-layer board; con- version to a six-layer FHE system requires at least 12 screen printing processes, including six for the conductive ink and six for the di- electric ink, which makes the process develop- ment very expensive. Other challenges to be dealt with for a six-layer substrate are higher thickness, less flexibility, and misalignment of conductive ink and dielec- tric ink layer to layer. The other option is to use a single layer of con- ductive ink to route all the processor pads. However, this requires fine-line ink printing, considering the space between the pads is only 150 µm. If one trace passes through two neigh- boring pads, 50 µm lines and spaces are needed; if two traces pass through, 30 µm line/space are need- ed. In the previous proj- ect, we have demonstrat- ed our capability by print- ing conductive ink in 50 µm line and space in the lab environment. Howev- er, printing 30 µm lines/ spaces with consistent quality still requires sig- nificant process develop- ment. Printed conductive ink typically shows much higher electrical resistance as compared to the con- ventional etched copper trace. Printed ink in the fine line will make the electrical resistance even higher, which makes it very challenging to satisfy the high-frequency system require- ment. Working with the design team, we eliminat- ed some of the pinouts of the LGA package for escape routing by simplifying certain func- tionalities of the system. We were able to use the two-layer structure of the printed ink. For this, we also have two options. One is to build up the interconnect structure layer by layer, by printing conductive ink first, then dielectric ink, followed by conductive ink then dielectric ink. The other option is to print conductive ink on the top and bottom of the flexible substrate and use filled microvias to connect the top and bottom inks. We have projects ongoing to pur- sue both approaches, but for this article, only the latter one (microvia) is presented. Figure 1: Footprint of the LGA package.

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