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JULY 2019 I PCB007 MAGAZINE 37 Future Work One of the major drawbacks of this energy level approach derived from the fact that the maximum g-force is not able to compute the accumulated stresses so as to understand the damage from accumulated energy to the inter- connect system of contact and solder joint. The research teams are looking forward to adding the lab rolling rock test to emulate the accumu- lation energy for railway and sea cargo routes then compare to the shock energy accumulat- ed over time in these two routes by integration the area under the g-force time curve. The iNEMI Board Assembly Technical Road- map of 2017 predicts that the low-temperature soldering (LTS) usage will increase to 20%+ by 2027 [3] . The drivers for this LTS technology trend are threefold: the energy and CO 2 emis- sion reduction, overcoming the material limita- tion in electronic components and PCBs, and low-temperature soldering process to match with electronic miniaturization. Due to the nature of the brittleness of bismuth contained in the low-temperature solder SnBiAg, the im- pact-related failure rate of LTS is substantially below current SAC305, which is widely used. Potential mechanical strengthening mecha- nisms, such as corner or edge bonding mate- rial attached along the BGA, are been evalu- ated to reduce the susceptibility to mechanical shock. Since some of the BGAs still use SAC lead-free solder, there will be forward compat- ibility issues with LTS paste applications to the SAC component circuit interconnect system. The mixture of SAC and SnBiAg creates a com- plicated mixed alloy system in which bismuth tends to form a layer in bulk the form in the mixture as well as along the IMC and solder interface (Figure 11) [4] . It is the intention of the project team to use the energy level approach to evaluate the LTS solder joint interconnect integrity when the product packages are going through the same shipping routes. PCB007 References 1. P. Wang, D. He, G. Mai, D.F. Chung, D. Kearns, "The Re- alization of Big Networking and Cloud Computing Dream From Contact Interconnect Methodology to Process Tech- nology," Proceedings of ICEPT/IEEE Electronic Packaging Technology, August 2016. 2. IEC 60068-2-27, "Environmental testing—Part 2-27: Tests—Test and Guidance, Shock." 3. P. Wang, et al., "iNEMI Board Assembly Technology Roadmap TWG 2017," iNEMI Board Assembly Technology Roadmap (Edited Report), 2017. 4. P. Wang, D. He, V. Cao, G. Mai, S. Song, F. Ge, K.G. Tan, "Interconnect Reliability of Low-Temperature Solder for Potential Application in Enterprise Computers, Portable, and Automotive Electronics," Proceedings of ICEPT/IEEE Electronic Packaging Technology, August 2018. This paper was first presented at the IPC APEX EXPO 2019 Technical Conference and published in the 2019 Technical Conference Proceedings. Dr. Paul Wang is VP of technology engineering and global quality. Vincent Weng is senior engineer of reliability engineering. Dr. Kim Sang Chim is senior manager of reliability engineering, all with MiTAC International Inc. Figure 11: Microstructure of mixed alloy of SnAgCu and LTS (L) with IMC thicker at package side (upper R) and bismuth accumulation at LTS and IMC interface (lower R).