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PCB007-July2019

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74 PCB007 MAGAZINE I JULY 2019 testing had to make do with a learned com- parison test on a sample from the build lot. The risk that the sample board was bad was significant, setting up the age-old "two wrongs make a right" scenario. For example, if the board had a repeating film defect that affected the entire lot, the learn comparison test for ET would have been performed on a bad board. As would be expected, when a bad board is learned and tested against an entire lot of bad boards, they all "pass." More than once, this false-premise test data resulted in catastroph- ic failures at the assembler and a 100% reject back to the manufacturer. Complicating matters in the '80s were the challenges of ET verification. The fixture or grid testers of the day supplied fault data in an X-Y grid coordinate system based on the test fields of the machine. The fixtures used pins that matched the footprint of the PCB and translated down to the X-Y grid where the ma- chine learned the electrical signature of the board. When opens or shorts were detected, they were reported in the X-Y grid. This results data had to be translated by hand to identi- fy the locations on the board where the fault was reported. This was usually done with the help of a mylar grid overlay that the inspec- tors placed over the board and a datum point identified on the fixture to match to the PCB. The difficulty for the inspectors was in proper- ly identifying the locations on the PCB that the machine had reported. Multimeters or "beep- ers" were used to ring out the probable fault and determine whether it was an open or a short. This methodology was risky and could easily lead to misdiagnosing a fault, which would then result in an escape. Netlist Testing With the advent of netlist testing, it became possible to develop tools to graphically iden- tify the reported fault locations on the board based. Electronic "to-from" lists were now available to translate the fault data from the test machine's X-Y grid to the actual PCB de- sign. These methods were primitive at first but got the job done with a much greater degree of accuracy than the old overlay method. Enhancing the quality process is a significant advance in verification. Gardien's FaultStation is a prime example. FaultStation is designed to seamlessly provide real-time fault verification based on the machine reports, either fixture/ grid test or flying probe. In today's ET arena, data is key. In Gardien's case, we receive the tooling data from the manufacturer. Sometimes, that tooling may be just the raw customer data, or it may be post-process tooling data from the manufac - turer. But what is new at this point is that the OEM's electronic netlist is also provided. With a netlist, ET will create the test solution from the manufacturing data and then compare the electrical signature solution to the OEM netlist. This process validates that 1) the ET program data is correct with respect to the OEM require - ment, and 2) there were no errors introduced during the manufacturer tooling process. Figure 1 depicts the Gardien design process flow. Remember, "garbage in, garbage out," so the proper feedback and check process is es- sential. The Gardien ET process reviews the customer/OEM requirements as well as the in- dustry specification(s) that may also be nec- essary; this includes IPC and military require- ments as applicable. This also ensures the proper test methodology and test parameters are used when testing the product. The test equipment will now log their fault data to databases for result retention. FaultSta- tion, for example, utilizes these databases to quickly load fault data from the machines and uses the design data to visually present the faults to the verification operator. Using bar- codes from the test machines, the fault report from the machine can be scanned by FaultSta- tion. FaultStation queries the machine data- The risk that the sample board was bad was significant, setting up the age-old "two wrongs make a right" scenario.

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