Issue link: https://iconnect007.uberflip.com/i/1153097
74 DESIGN007 MAGAZINE I AUGUST 2019 the ±5% tolerance of the 1.2V power source specified in the data sheet of memory IC. Thirdly, the eye diagram of the DDR4 data signals at 1 Gbps with PRBS-7 bit sequence (observed at Rx or SoC) is compared for PDN condition A versus D, as shown in Figures 4a and 4b respectively. A much larger eye height and width experienced by data signals in con- dition D indicates that the suppression of SSN due to improved power integrity helps reduce the jitter in the signals transmitted by the memory IC. The shrunken eye diagram open- ing suffered in condition A increases the risk of bit error and metastability at Rx IC. The sup- pression of SSN is achievable by properly plac- ing sufficient decoupling capacitors on power rail with reference to ground. Summary The post-layout co- simulation of power and signal integrity demon- strated in this article in- dicates that placement of sufficient decoupling ca- pacitors on a power net with reference to ground has a positive impact on PDN impedance, SSN, and eye diagrams. Addi - tionally, prerequisite sig- nal integrity simulation must be conducted on the signal lines of inter- est to ensure the optimal termination scheme and minimal transmission loss before the co-simu - lation to analyze the mu- tual effect of power and signal integrity. DESIGN007 References 1. B. Olney, "Power Distribu- tion Network Planning," The PCB Magazine, May 2012. 2. F. Carrio, V. Gonzalez, and E. Sanchis, "Basic Concepts of Power Distribution Network Design for High-Speed Trans- mission," The Open Optics Journal, 5, (Suppl 1-M8) pp. 51– 61, 2011. 3. E. Bogatin, Signal and Power Integrity—Simplified: 2 nd Edition, Prentice Hall, 2009. 4. Mentor HyperLynx, "Power-Aware Signal Integrity Analysis." 5. Micron, "Power Integrity Simulation With IBIS 5.0 Models Technical Note." Chang Fei Yee is a hardware engineer with Keysight Technologies. His responsibilities include embedded system hardware development, and signal and power integrity analysis. Figure 4a: Simulated eye diagram of the DDR4 data signal for PDN condition A. Figure 4b: Simulated eye diagram of DDR4 data signal for PDN condition D.