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78 PCB007 MAGAZINE I AUGUST 2019 parison between a new SAP PCB process and a conventional SAP PCB process. Introduction The improvement in semiconductor density by miniaturization has progressed in recent decades as described by the famous Moore's law—and it is still progressing today. The semiconductor components are assembled on an interposer called a package substrate. The package substrate allows those components to mount to a base printed circuit board (PCB) using inexpensive soldering technology. When the semiconductor size decreases, the package substrate size is also decreased. The related PCB feature sizes then also follow with the same scaling factor. The semiconductor miniaturization brings significant economic and technical benefits and the semiconductor scale factor becomes the master for the associated package and PCB design. The semi-additive process (SAP) has recently been developed for fine-feature PCBs. However, this is mostly utilizing the thin copper foil base process because of concerns around copper adhesion to the base material. This ar - ticle describes a new SAP utilizing chemically plated copper for the base conductor. SAP Process and Base Copper SAP is basically the same process concept using the panel pattern plating method that is commonly used in North America PCB shops. However, unlike subtractive processes, with SAP, the copper plating is selectively applied only to the pattern, resulting in thinner Cu to be etched away. The first step is the base copper preparation using a copper foil and a plated copper. The second step forms a plat- ing resist with a negative pattern over the base copper. Then the third step plates up the cir- cuit copper. The fourth step is the plating re- sist strip, and the last step is a quick etching of the unnecessary base copper (Figure 1). The intention of this process is to get bet- ter pattern accuracy than with the subtractive process due to less copper etching. Copper etch in the PCB process is a wet process us- ing an etching solution. The etching proceeds as an isotropic reaction and not like an aniso- tropic gas phase silicon etching. The isotropic etching ruins pattern accuracy due to differ- ent etching amounts between the initial area (copper top) and last area (copper bottom). Therefore, less etching provides higher accu- racy of the pattern geometry. The other benefit of this process is the electrolytic plate for cop- per growth. It provides a shorter process time and a better economy for manufacturing. A type of fully additive process places a permanent plating resist over the catalyti- cally active substrate and then plates copper on the exposed catalyst to form the circuitry. This is usually plated copper utilizing electro- less plating. This gives circuit uniformity, but the process time and cost are higher than the electrolytic plating method. The fully additive method can also utilize electrolytic copper de- position, but it limits the circuitry design due Figure 1: SAP process flow.

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