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OCTOBER 2019 I DESIGN007 MAGAZINE 55 companies are looking to maximize package assembly efficiencies are fabricating panels as large as 600 mm 2 . Glass Interposer Base Material Significantly less costly than silicon, glass panels are being supplied by a number of companies specializing in manufacturing a physically durable glass with properties suit - able for 2.5D interposer fabrication. The via hole forming processes for glass includes la- ser (CO 2 , excimer, nano-second UV, pico-sec- ond UV, and femto-second UV) and electro- static discharge (ESD) as well as mechanical drilling using micro-sandblasting. Metaliza- tion on glass begins with a vapor deposition (PVD) process of copper or silver ink deposi- tion to furnish the base for filling vias and in- terconnect circuitry. Glass is available in panel thicknesses that range from 50 µm to ≥700 µm, and the pro- cess differs significantly from silicon wafers because it will not require back-grinding and polishing before via ablation and plating oper- ations. The nominal CTE of the metalized glass panel is also a very close match to the silicon die (3 ppm/°C). This ensures that the 2.5D interposer and attached die elements exhib- it a uniform CTE, eliminating physical strain where the elements are joined. Regarding glass panel shape, currently, panels up to 500 mm x 500 mm are being developed to be compatible with established PCB assembly placement and joining processes. Presently, there is a global effort by mem- bers of Semiconductor Equipment and Materi- als International (SEMI) to develop standards for manufacturing 2.5D-compatible panels. The standards will establish panel size varia- tions, thicknesses, and surface topography as well as panel warpage limitations. Part 2 of this column will focus on design guidelines for the three 2.5D interposer variations noted here and detail methodologies for both simple and complex component interconnect. DESIGN007 Vern Solberg is an independent technical consultant based in Saratoga, California, specializing in SMT and microelectronics design and manufacturing technology. To read past columns or contact Solberg, click here. Figure 2: Basic process flow for metalizing and preparing plated through silicon via (TSV) holes for the 2.5D interposer.