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70 PCB007 MAGAZINE I OCTOBER 2019 For the simulation of the stitching element, we have set up the element shown in Figure 2: a VeCS-2 (blind) element with eight connec- tions—seven connections on one side and a GND reference on the opposite side of the slot, creating a reference to the seven connections. For visibility purposes, we have not drawn all of the reference layers. The five connections consist of: 1. A differential pair 2. GND (purpose shielding) 3. A single-ended signal 4. GND (purpose shielding) 5. A differential pair The GND reference creates controlled im- pedance for the differential pair. The topside of the differential pair VeCS section is back rout- ed to minimise dispersion. In Figures 3 and 4, we also show the second route features. The dimension of the router bit used for the second route, top back route, and bottom route is 0.3 mm. All of this routing is done in the same process step. The element created sets up a buried mi- crostrip for the differential pairs and the sin- gle-ended trace. The trace width used in this example is 0.12 mm; depending on the stack- up, this can be tuned to the required differ- ential impedance. The vertical trace width is 0.30 mm. This will yield a buried microstrip construction and an impedance of ±110 ohms (ZOdd). We took into account an Er of 4.0 for the slot filling material. The stub length is defined by the length below the trace and the part of the slot that is left over after removing the bottom of the slot (Figure 6). We have set a maximum stub length of 0.125 mm + 0.1 mm = 0.225 mm on the bottom side. Figure 2: Simulation of the stitching element. Figure 4: Top view showing the bottom rout (BR). Figure 6: Stub length. Figure 5: Vertical and horizontal trace width. Figure 3: Top back rout.