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82 SMT007 MAGAZINE I NOVEMBER 2019 would prevent molten solder from wicking down the vias while allowing volatiles devel- oped during solder reflow to escape and min- imize the size of the voids at the thermal pad of the BTC. The follow-up questions were if the void size would vary when solder is printed intentionally over such exposed via in pad, and how it would compare with the case when the solder paste is deposited between the exposed vias. Starting from the hypothesis, Figure 1 shows a brief review of the force equilibrium of a finite volume of solder emerging in an exposed via- in-pad; the height of the solder column turns out to be a function of the contact angle and the size of the finished via. Figure 1 assumes the case of a wettable surface inside the PTH. At equilibrium, the height (h) of the solder column is described by Equation 1: From a soldering application viewpoint, Equation 1 has no practical application; when solder reaches the TH exposed via, solder will wick down the via according to the wet- ting ability, amount of the solder available, and heating/cooling conditions. However, it is interesting to use Equation 1 and question what conditions would allow the height of the solder column to be minimized or made zero: • If the solder does not wet the via (via not plated) • If q 1 = q 2 (absence of gravity) • If q 1 = q 2 = 90° (cannot be a natural solution) Since these three conditions cannot be sat- isfied for exposed plated through vias, and due to the relationship between the supposed height of the solder column and the radius R of the exposed plated via, it seems unlikely that it is possible to prevent solder from wick- ing down a wettable plated via for any via size, regardless of how small its practical fin- ished size diameter may be. Back-of-the-enve- lope calculations aside, a practical verification is required to fully verify the hypothesis. For this purpose, a test vehicle was designed and parameters calculated as described in the fol- lowing section. Experimental Findings Test Vehicle The experimental approach was to design a test board having various PTH via diame- ters and via arrays, design the stencils such that solder paste is either printed over vias or between vias, fabricate the boards with differ- ent thicknesses, and after assembly, tally the vias with solder, void percentage, and the sol- der protruding from vias. If the hypothesis is proven, then voiding in the thermal pad is minimized, heat transfer is optimized, and the components will pres- ent uniform solder joints stand-off height. Oth- erwise, the factors leading to solder wicking down the exposed vias could be the following: • Volume and location of the printed solder • Solderability of the finished via • Solder wetting ability • Presence of barriers (solder mask webs) • Temperature values and temperature gradients Figure 1: Equilibrium of forces acting on a finite volume of solder inside an exposed via.

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