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NOVEMBER 2019 I DESIGN007 MAGAZINE 61 Power consumption in FPGAs has also become a primary factor for FPGA selection. Whether the concern is absolute power consumption, usable performance, battery life, thermal chal - lenges, or reliability, power consumption is at the center of it all. To reduce power consump- tion, IC manufacturers have moved to lower core voltages and higher operating frequencies, which means faster edge rates, of course. And faster edge rates mean reflections and signal quality problems. The enhancements in driver edge rates have a significant impact on signal quality, timing, crosstalk, and EMC. Figure 4 illustrates the change in edge rates over the years from 30 ns back in the early 1980s to less than 1 ns in 2010. Sub-nanosec- ond rise times are now common. For the same frequency and length trace, the faster edge rate creates ringing in the unterminated trans- mission line. This also has a direct impact on radiated emissions. Figure 5 shows the mas- sive increase in emissions from the slowest to Figure 4: Edge rate changes in the time domain over the years (simulated in HyperLynx). Figure 5: Radiated emissions in the frequency domain from 10 ns edge rate (L) and 1 ns (R).