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96 PCB007 MAGAZINE I NOVEMBER 2019 Fine-line/Tight-registration Image Transfer and Etching 1. Investment in laser direct imaging 2. On-line pH control and replenishment of developer solution to maintain a very narrow pH range 3. For fine lines, consider SAP (semi-additive processing either with thin dielectrics, such as resin, film, or etched-off copper from laminate) or subtractive etch to reduce copper foil thicknesses 4. Improved rinsing modules especially for tight spacing and very small vias 5. Horizontal equipment set-up for thin material transport 6. Critical control of fine-line imaging and etching These six areas are crucial for the fabricator to consider to be successful in meeting these new requirements. And with respect to the re- quirements for finer lines and spaces (along with minimal undercut from etching), semi- additive or modified semi-additive technology takes center stage. The issue currently acting as a significant roadblock is the lack of expertise in this area. Yes, there is some semi-additive processing in the industry, but certainly not enough to achieve what one would call "criti- cal mass." For technology implementation to be successful, it must be widespread. That is where there are many sources of the technol- ogy, both from the pro- cess supplier side as well as the fabricator. Stacked and Staggered Blind Vias Perhaps the most sig- nificant change over the past few years is the proliferation of the use of blind vias, including multilevel blind vias. Further, many design- ers require these multi- level vias to be stacked (Figure 2). In Asia, the use of stacked vias is consider- ably higher. While this design has many advan- tages in supporting technology, including IoT, sensors, and AI, the ramifications related to the thermal reliability of these vias have been called into question. There has been much re- search lately fostered by HDPUG (HDP User Group) as well as the IPC Technology Solu- tions Committee and its subcommittee, which is the TSL-MVIA Working Group. In a nutshell, it is this that keeps that me awake at night. With so many moving parts to this technology related to these complex board builds, a solu- tion remains elusive. The use of stacked and copper-filled vias has proliferated over the past three years. This is driven primarily by the need to increase rout- ing. Thus, the move from staggered multilevel vias to stacked and filled vias for many of these designs. However, what was not anticipated was the latent defect shown in Figure 3 [1] . Essentially, as Figure 3 depicts, there is a hidden defect that is not normally detected by in-circuit testing. This defect, described as a weak interface between the electroless copper deposit and target pad, manifests itself most often during convection reflow assembly; however, that is too late, or the defect leads to a failure when the interconnect device is in service. Regardless, this is a critical situation that requires all hands on deck to fully under- stand the root cause or causes of this latent Figure 2: Increased used of stacked vias. (Source: IPC)

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