Issue link: https://iconnect007.uberflip.com/i/1185676
94 PCB007 MAGAZINE I NOVEMBER 2019 One does not have to look too far back to point out some significant changes that have taken place in our industry over the past few years. Processes, materials, equipment, and board designs continue to change. If I was to pick one to focus on for this column, it would be in the ever-increasing trends toward higher circuit density. This relates to finer lines and spaces, smaller diameter blind vias, and even multilevel stacked and staggered vias. All of these changes will continue to place signifi- cant pressures on bare PCB fabricators to in- crease their investment and onboard new and critical skill sets. What Is Driving These Changes? The semiconductor packaging industry is driving changes to higher density for both the bare board as well as IC substrates, system inte- gration, SiP, and very- large-scale integration (VLSI). Increased device complexity has been a primary driving fac- tor for future designs. To keep the component package size small, com- ponent lead spacing was decreased. Further in- creases in semiconduc- tor integration (VLSI), requiring more than 196 I/Os, can drive packages to even closer perimeter lead spacing such as 0.5 mm, 0.4 mm, 0.3 mm, and 0.25 mm. The array package format has become standard for high I/O count devices. To support these requirements, wiring density is increased. Looking at the latest data from various road- maps, one can easily see the following: • Finer lines and spaces • Increased use of blind via technology • Stacked vias What challenges are bare board fabricators facing? Look at the first bullet point. The aver- age minimum line width and spacings as spec- ified by OEMs are shown in Figure 1. As the line width and spaces become finer and tighter, several opportunities for change present themselves. Changes and Concerns Regarding HDI Technology Trouble in Your Tank by Michael Carano, RBP CHEMICAL TECHNOLOGY Figure 1: Minimum line width and spacing. (Source: IPC)