Issue link: https://iconnect007.uberflip.com/i/1221561
96 PCB007 MAGAZINE I MARCH 2020 the vacuum encapsulation, which has also been around for a while. It always came back to, "Is the interconnect going to pull off?" because it's a trace down the sidewall of the slot. All of our early test vehicles were built around doing extensive thermal cycling, stress- ing it as much as we could; that's how we broke through-hole and HDI interconnects to understand the process in lamination. WUS has some pretty sophisticated algorithms for doing CTE expansion for both HDI structures and through-holes, where we can identify the weakest points in the design and the materi- al set by glass filler type, resin type, and then the design features that are built around it. We have done four years of work on it. We already knew where the breaking points were for ma- ny different types of laminates and intercon- nects. We started working on that and found that when the VeCS interconnect was encapsu- lated in a similar CTE material to the laminate, the pressure point or stress point of breakage was not near the interconnect like it would be a through-hole, or at the base of a via like it would be with HDI. It's the elongation of the trace, and because it's fairly uniform around the trace, the ex- pansion and contraction are similar to what it would do on an outer-layer signal. The electro- lytic copper we used had 14–17% elongation, so it took a lot to even attempt to break a VeCS signal. Johnson: Doesn't that sidestep some of the critical issues right now with HDI? Dickson: That's true. Where we're at right now is the industry is evolving in buildup technol- ogy and the maturity of HDI. I started working on HDI in 1992, and both mechanical and la- ser- formed vias have been around forever, but it's still relatively new to the large format BGAs. This application exposes concerns during ther- mal cycling primarily because of the issues of CTE mismatch between the plated solid copper via and the anti-pad area immediately next to the via. There are tricks that you can do, like IBM did, where you take two layers stacked, and then stagger them. We have even built a model where we can tell, in mils, how much expansion is happening near areas, and we can modify the design and materials to minimize stress on an HDI buildup. However, whether it's four, five, or six lamination cycles, at some point, you're put- ting extremely high stress on the single point of contact of the electrolytic plating to the capture pad and the source of either electroless or direct plate that you used. That's very difficult. That's very high stress on that key contact. Usually, when it fails, it fails completely. You will see it separate. We have never seen it with VeCS. We've done 20 thermal cycles at T260, where the through-hole would have fallen apart, and HDI pads lift com- pletely off, but the VeCS doesn't break. We have run it enough and cooled it quickly, as well as run it where we had the trace crack. It's so far beyond what traditional is that I feel pretty con- fident that the interconnect in this application is going to be a pretty high part of the reliability. We also have techniques on how to form in- terconnects, and we can even make a three- sided VeCS connection, but the real benefit that people want with VeCS is that you can match the impedance down the sidewall of the sig- nal layer. If you have 85 ohms running on the trace, you can match the 85 ohms down the sidewall and then come back in. That imped- ance continuity seems to be especially valu- able for high-performance computing and PCI express applications. Johnson: You talked a little bit ago about elon- gation to trace with respect to VeCS. To be clear, is that along the surface of the board? We have done four years of work on it. We already knew where the breaking points were for many different types of laminates and interconnects.