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52 DESIGN007 MAGAZINE I MAY 2020 For very fine pitch (>3.0 mm) applications, the developer may employ a secondary selec- tive plating process to form raised, solid cop- per terminals. The so-called "micro pillar" is significantly smaller in diameter than the ball or bump variations, enabling a considerably narrower (<0.3 mm) terminal pitch. Multiple-die FOPLP Other process variations have naturally evolved, including multiple-die configurations. The benefit of clustering and interconnecting two or more associated heterogeneous or ho- mogenous semiconductor die within the con- fines of a single package outline enables very close coupling and the potential for enhanced electrical performance (Figure 4). The target package outline for a broad number of wear- able and wireless products is 100 mm 2 to 140 mm 2 . Ide- ally, the die elements select- ed for both single and mul- tiple-die applications will be able to achieve equivalent finished package outline goals while maintaining the uniform terminal pattern re- quired for efficient PCB-lev- el circuit routing. Although the interconnect design pro- cess may initially remain within the package developer organizations, PCB design special- ists will likely have the opportunity to contrib- ute their talents as well, especially in develop- ing the multiple-die FOPLP configurations. Design Rules for FOPLP In regard to design rules for single and mul- tiple-die package applications, those currently familiar or becoming familiar with high-den- sity additive and semi-additive circuit design criteria will be prepared to put their talents to good use. It's really a matter of scaling. The de- sign guidelines furnished in Table 1 illustrate the expectations for interconnecting semicon- ductor die in the FOPLP format. Because process capabilities will often vary between one supplier or another, the circuit density and feature sizes noted in Table 1 may be more or less than those factors shown. Be- fore beginning the development of the fan-out circuit interconnect pattern, the designer is ad- vised to confirm compliance with the manu- facturer's imaging and plating capability. Qualification Testing With shorter development cycle time and more frequent introduction of new package technologies, a comprehensive qualification methodology will remain paramount in order to identify reliability weaknesses during the qual- ification of new package variations and mate- rial sets. A study by members of iNEMI (Inter- national Electronics Manufacturing Initiative) consortia [2] concluded that "New integrated Figure 4: Heterogeneous three-die FOPLP. Table 1: General design guidelines for FOPLP.

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