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50 DESIGN007 MAGAZINE I MAY 2020 land pattern features on the opposite surface of the wafer (Figure 2). The die elements terminated on the wafer's upper surface are frequently encased with a polymer mold compound followed by solder ball or bump terminal formation, marking, and singulation to enable unit-level electrical testing. Fan-out, Panel-level Packaging (FOPLP) The semiconductor package development specialists are always striving to find solu- tions for improving manufacturing efficiency and trim manufacturing costs. Although the FOWLP process has proved robust and reliable, the cost associated with silicon-based interpos- er fabrication has been a primary roadblock. In the effort to trim overall packaging expense, a number of alternative packaging methodol- ogies have emerged. Both independently and through consortia between academia and in- dustry, several viable solutions have evolved that provide the same fan-out interface with- out the need for a silicon wafer as a base. Panel-level package development utilizing alternative, lower-cost base materials actual- ly began prior to 2016 to address several high volume market segments. By 2019, four promi- nent supply sources in Asia—Powertech, Sam- sung, and Nepes—had already achieved vol- ume-manufacturing capability followed by ASE Group beginning production in early 2020. The timetable for additional offshore and domestic companies' availability of FOPLP in volume is forecast for 2021 and 2022. FOWLP vs. FOPLP When compared to the silicon-based FOWLP, developers implementing the panel-configured process have realized significant cost savings, greater process efficiency, and the economies of scale. Equating the high material cost of sili- con wafers to the significantly lower-cost panel material is a key issue, but the greater die pop- ulation potential for panel-level processing has proved most beneficial. In regard to establishing standards for the basic panel structure, several manufacturers and material supplier members of SEMI (Semi- conductor Equipment and Materials Interna- tional) 3D Packaging and Integration Technical Committee have developed SEMI 3D20-0719, which is a specification for panel characteris- tics for panel-level packaging (PLP) applica- tions. The organization's position is that "stan- dards increase industry efficiency by reducing or eliminating duplication of efforts, help to define new markets, and promote competition by lowering barriers to entry." The purpose and scope for the SEMI PLP specification were written to include four pro- cess-compliant base materials for carrier pan- els and establish standard panel dimensions. Revision A of the document (currently submit- ted for member approval) establishes two stan- dard panel sizes: 510 mm x 515 mm (~ 20" x 20.3") and 600 mm x 600 mm (~ 23.6" x 23.6"). The four optional base materials noted for carrier panel preparation are glass, silicon, ceramic, and metal; however, silicon and ce- ramic materials have a significantly higher ma- terial cost. The semiconductor-packaging specialists will select the material and panel size that will best meet their particular assembly, molding system, and plating process capability. In re- gard to panel size, the half-panel may be more suitable for processing within the commer- cial circuit board manufacturing environment while a quarter-panel size will likely be most compatible with semiconductor wafer process- Figure 2: FOWLP (die-on-silicon).