Issue link: https://iconnect007.uberflip.com/i/1295812
OCTOBER 2020 I DESIGN007 MAGAZINE 39 Horner: These are the RDL layers that I was describing around two microns. The pack- age substrate material is also referenced as organic, but that is different than an interposer organic, which tends to be referenced to more of an RDL layer that is used for die to die con- nection. Johnson: We're now talking about having a semiconductor package that has multiple chips of different capabilities, plus an interconnect using different kinds of interposers. The inter- poser design is essentially a PCB that goes in the middle of the package. Is this interposer considered an IC design item, or is this a PCB design that then ends up inside the chip? Horner: There are different materials used for the interposer. The most used interposer today is the silicon interposer. There's also glass that was mentioned earlier. Historically, a package did not have to deal with a lot of the complexities needed in today's multi-die integration. That's why a lot of these tools that were typically used for package substrate design are running out of bandwidth and capabilities for complex multi-die designs. Using EDA tools optimized for complex SoC design is more optimal in addressing silicon interposer design needs. Some vendors are trying to approach it from the package side, and they get a lot of complaints from custom- ers and the people that we're interfacing with, saying, "They're out of juice. They don't have the bandwidth." How do you do the modeling for your signal integrity analysis? How do you do your model- ing in terms of power integrity analysis? How do you bring the information together from dif- ferent technologies? Even the silicon EDA tools are not capable of doing that because, usually, when you design one IC, you deal with one technology at a time. It's 14 nanometers. You need a more enhanced tool environment that allows you to integrate multiple technologies now to be able to model them, analyze them, do analysis, and validate them in the multi-die environment. Johnson: This inserts a different domain of knowledge into the IC design team's area of responsibility. Horner: That's why I was mentioning the need for a collaborative environment. It's not just IC design's problem. It's not only the packaging design person's problem or a signal integrity problem. All disciplines have to work together to make this problem be more optimally addressed. Johnson: Is this where PCB design experi- ence becomes valuable to the IC team? Is this a place where you'd want to start bringing in Table 1: Substrate interconnect scale roadmap (micrometers). (Source: HIR, 2019)