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32 DESIGN007 MAGAZINE I NOVEMBER 2020 Class 3 products. If you have two terminations of line vias and then a through-hole filled via and then through-holes, you already have a mil and a half of wrap required on the surface of that layer. And if you're trying to etch fine lines and spaces, including through-hole plating, then you just end up with way too much copper. Especially in the RF world, you want to model with the expected amount of copper on the surface, and nobody really needs three or four mils of copper on there for RF technology. There's a lot of thermal technology people who want three-ounce or four or five mils of copper on a surface, but that's a different group. Believe it or not, the demand for it is not as high as we would have thought. I think it's because we've taught our customers to call out the right specification. If you're building an RF board, go with IPC-6018—not IPC-6013, which is for analog and digital boards. It's not really intended for RF products. Once we get past that minimum requirement of a half mil of copper wrapped on every termination of a subassem- bly or filled via set, then things move better. And I could debate the reliability of having half mil of wrap around a plated through-hole and whether that's any stronger than two-tenths. That's one of those ongoing debates that's similar to etchback. There are those who say positive etchback gives you a better interface for internal layers and others who say negative etchback gives you a better interface. Shaughnessy: Are you still doing some funky boards for autonomous vehicles? Hofer: We have several customers in the auton- omous vehicle realm. It's funny because we have three of the bigger players. They'll say, "We want to do this and that," and it's so diffi- cult not to say, "We have some ideas," because, obviously, you can't share those. Shaughnessy: For autonomous vehicles, you want reliability. What kind of via processes are you using typically for boards for autonomous vehicles? Hofer: We are starting to stack quite a bit for one of the players. Another player has a whole different technology, but for one of them, we're starting to stack and stack. We've just been tasked with taking a 12-layer and making it all stacked microvias, which would take us over five per side, and I'm recommending against it. But to fit in the real estate and to get the chips on it that they want, we have to discuss it. It will be interesting. Shaughnessy: You must do a lot of your own research on this. Hofer: We do test some ideas and processes. I don't want to say too much, so we do lots. We work together to run some sample boards and have them tested. I started having a lot of people ask about our surface roughness, and until recently, we never sent out for surface roughness testing. Why would we? Now, I'm constantly looking at what processes cause a certain amount of roughness and what the end result is because that's becoming more and more a topic of concern. Holden: The vertical conductive structure (VeCS) process gives you a microvia density without laser drilling. It's great for your PTFE boards because you can get microvia density, but you don't have to use a laser drill, and you only need one lamination instead of sequential laminations to connect to different layers. You rout in slots in the board, and with the slot, after metallization, you can connect to any layer, anywhere along the slot, up or down. You can make a slot all the way through the board, If you're trying to etch fine lines and spaces, including through-hole plating, then you just end up with way too much copper.

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