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60 PCB007 MAGAZINE I NOVEMBER 2020 There are some options in ET that can be add- ed to reduce the risk of rejection once the prod- uct leaves the manufacturer (Figure 2). Forced Barrel Test Although Class 3 Level C products do not al- low the optimization of mid-points, it is not specific on how the mid-point is tested. Most ET rasterization routines will follow the circuit from end-to-end and place test points at the endpoints. If optimization is not allowed, the system will place test points at all intermedi- ate test points along the net. However, this is based on the accessibility of the mid-points. The drawback is that if a mid-point is a via, it may test one side or the other depending on the accessibility (solder mask). When one side of the via is covered, it's straight forward; the open side receives a test point. The lottery here, though, is if both sides are clear most systems will place the test point on one side or the other randomly. The vul- nerability here is that if the test point is placed on one side and the assembly house uses the same via as an in-circuit test (ICT) point but probed from the other side, the standard ET at the manufacture can pass, but the ECT test at the assembler can fail. How can this be? The answer is that the test on the ICT side of the via could be voided. The barrel on the ET side may still be intact and pass the cir- cuit through the interconnect(s) but is voided above the circuit path. This is undetectable in standard ET, even with mid-point optimization removed. The mid-point is tested, and the cir- cuit is valid. However, the ICT test fails. In reality, the board is fully functional but cannot be verified at the assembler and is therefore rejected. What we can do is force the barrel test. Regardless of the standard test, the barrel test can be added. Once the barrel test is activated, the user can select the drill size or the range of sizes to be checked. Now, there are some requirements for the forced test to be of value. As I stated previously, both sides of the bar- rel must be accessible. This is a straightfor- ward continuity test based on the parameters selected for the full test. This option just forces the side-to-side barrel test to capture the pos- sible electrical null area of a via void escaping. This test is not to be confused with 4-wire Kel- vin. This test option will capture full void sce- narios and not necessarily thin copper or taper plate conditions. 4-Wire Kelvin Kelvin 4-wire testing is all the buzz now in printed circuits. One of the most difficult de- fects to capture is the latent barrel void. It is common for this defect to hide and miss detec- tion during normal ET. Most ET specifications require continuity of circuits to pass at a min- imum of 5 ohms continuity at the stricter end of the spectrum (Figure 3). With plated drilled holes, the difference be- tween a conforming barrel and a non-conform- ing barrel will be in the milli-ohm range. The standard continuity parameters will not be able to detect these issues, as the difference in resistance will not be detected as it will be Figure 2: Contamination-induced voiding. Figure 3: Barrel check parameters.

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