Issue link: https://iconnect007.uberflip.com/i/1309864
34 PCB007 MAGAZINE I NOVEMBER 2020 and run such dense interconnects, there are lots of opportunities for them. Matties: For a company that embraces this technology, this approach opens up new mar- ket opportunities. I would think that there's a significant advantage to be on the front-end of this thing. Dickson: We've agreed that part of our issue is we've had to do our own design test vehicles. Almost every time that we do a functional or demonstrator test vehicle for an OEM, it's un- der an NDA. With the IP of how to use this, there are so many options that you can do. You can shield an RF signal on three sides com- pletely. There's no way to do that with either HDI or through-hole. The moment they discov- ered they could do that, they said, "You can't publish this. This is part of our IP." We had to develop our own test vehicles and demonstra- tors internally so that we could say, "Try this." Tourné: The interesting thing wasn't only the technology. We recently had customers who wanted a faster lead time. They don't want to do six or seven laminations for a product be- cause it extends the lead time dramatically. Can we do a single lamination, so I get my product faster using VeCS and its single lam- ination? The same product instead of HDI on six laminations. Matties: Compared to the tradi- tional HDI, you've really cut cy- cle time down quite a bit? Tourné: We're not in volume pro- duction to a great extent right now, but laser drilling is faster. With the whole cycle of imaging, plating, imaging again, and re- peating that six times, instead of doing that one time; lamination cycles take time as well. We've ended up pulling it down. Over- all, yes, you're faster. Your single step on routing is slower. Matties: Plus all the thermal stress you're putting on the board with multiple lam- ination cycles. Tourné: It's aging the material, and aging the material means the life of the material is shorter. Matties: In terms of reliability, how does this play into that conversation? Dickson: It's very design-specific with where we're at right now. But with the structure it- self, we've done enough work now that we've demonstrated, and there are some pictori- al examples of VeCS-1. We've done reliabili- ty testing on the interconnect structure itself, and once it's filled and encapsulated, It's ex- tremely reliable, potentially beyond that of a conventional through-hole. We've had people simulate and model why that's so, and they're going to write papers on that. But it's primar- ily because the plated interconnect is more like a trace than a circumferential via and the stress on the connection is less. The weakest area is the VeCS trace; thus, it will fail only af- ter it reaches maximum elongation, similarly to a via. The stress levels of it are just in the expan- sion of the trace itself around the resin. That allows the interconnect inside the board to have almost no stress. We've done 20 reflow cycles and have not been able to break that Double-sided populated boards are connected front-to-back using VeCS-2 construction.