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Design007-Dec2020

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54 DESIGN007 MAGAZINE I DECEMBER 2020 process, then it takes more time, people, mate- rial, and money. This is where board-level simulation cuts re-spins: A pre-layout simulation identifies issues in the conceptual stage so that they can easily be avoided, and the post-layout simu- lation catches the issues during the design process eliminating the potentially disastrous final stage changes. Of course, you also need to keep your eye on the ball during the entire design process, catching any small issue before it becomes a major problem. This is the most cost-effective way to design a board with fewer iterations rather than starting with the "find- and-fix" post-layout simulation approach. There are multiple facets to board-level analysis, including: • Stackup planning for controlled impedance, SI, crosstalk, and cost control • Dielectric material selection for manufacturing yield and high-frequency operation • Transmission line termination strategy • Floor-planning for critical components • Deriving layout routing constraints, including trace width, spacing, and delay matching • PDN optimization • I/O buffer and drive strength selection • Topology optimization • SI analysis to meet the design specifications, with respect to noise margins, timing, skew, crosstalk, and signal distortion • Estimated electromagnetic radiation The board stackup configuration is the most often overlooked issue in the early design stages. The majority of designers leave the stackup planning to deal with at design com- pletion, along with fabrication deliverables. Before starting a PCB design, you need to plan the PCB stackup and impedance to ensure that the selected substrate materials are avail- able from your chosen fabricator—a step that is regularly missed. Changing the stackup toward the end of the design process could mean changing trace widths and clearances to achieve the correct impedance, which could create a lot of unnecessary work. If you use the same materials that the fab shop stocks to build your stackup, then the impedance will be more accurate (Figure 1). If we just choose a convenient (virtual) number for core thickness, for example, then this may Figure 1: The dielectric materials library lists the fabricator's stocked materials (iCD Stackup Planner).

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