Issue link: https://iconnect007.uberflip.com/i/1327102
JANUARY 2021 I DESIGN007 MAGAZINE 43 A Formula for Estimating Layer Count Okay, now that we have a few guidelines to go by, we can start coming up with some num- bers. Now, you're probably thinking "Holy crap, that's a lot of work!" Yep, it can be, but each item is not that difficult by itself. And this gets you in a reliable ballpark for the number of layers that you'll need. I have not found anyone else willing to quantify and share a good formula for calcu- lating the number of signal layers needed for a design (Table 1). I did have such a formula once, but I lost it when a virus invaded my computer. So, let's create one with the infor- mation we have. Then, if you come up with more ways or things to add to this one, we can keep sharing so we don't lose it again. Ratio of Part Area/Bd Space: R = PA/BS The "usable" board space available is impor- tant. This gives you your first estimate of layer count needed. Some layout packages offer this ratio in the program after you import the footprints. If the ratio starts to get around 0.9:1, you're going to need some special via structures to get everything connected. As the ratio gets closer to 1:1, more layers become necessary to route the board. If you're going over 1:1, you'll need more surface area or lose some parts. If your ratio is equal to or less than 0.5, you will probably need only 1-2 layers to complete the routing. If all your routing and returns are on just the two layers, you'll need about as much space as the components consume to route it and not get too much noise. When the ratio is over 0.5, then we need to add more factors into our layer count estimation. Ls = (SP x TSR) + tVa 1/2 (BS) Then add in 2R + Power Planes needed + 2bVa (The 2R is for component placement area on the top and bottom layers.) There are more factors you may have to con- sider depending on how complex your designs get. This should get you in the ballpark. Plus, there are some additive processes that are coming out (Averatek's A-SAP TM process, for one) that will help to reduce the TSR and help to cut down on the number of layers needed. Then search for and read anything written by instructors like Rick Hartley, Lee Ritchey and Eric Bogatin for tips on how to structure these layers. Let me know if this works for you as well as it has for me. DESIGN007 Cherie Litson, CID+, is an IPC Master Instructor for EPTAC, and founder of Litson Consulting. Table 1: Information needed to create a formula for calculating the number of signal layers needed for a design. Figure 3: Planning the stackup of a multilayer PCB involves many design trade-offs.