Design007 Magazine


Issue link:

Contents of this Issue


Page 47 of 127

48 DESIGN007 MAGAZINE I JUNE 2021 Serial and parallel communications cur- rently and historically co-exist and serve many requirements of intrasystem and intersystem data exchange. For instance, a parallel clock SERDES combo is normally used to serial- ize wide data-address-control parallel buses such as PCI. e choice of method is usually a tradeoff on factors such as speed, cost of materials, power consumption, and difficulty of physical implementation. In principle, parallel communication is intrin- sically faster than serial, because the speed of a parallel data link is equal to the number of sym- bols sent in parallel times the symbol rate of each individual path. Doubling the number of symbols sent at once doubles the data rate. For this reason, parallel communication is widely used in internal buses of integrated circuits and short distance IC-to-IC links. However, parallel communication is being replaced by serial communication in high-speed data links. ese links include IC-to-IC communications on backplanes, computer networks, computer peripheral buses, long-haul communications, etc. e conventional reason to choose serial communications instead of parallel communi- cations is cost. High-speed SERDES devices are the domi- nant implementation of I/O interfaces at speeds of 2.5 Gbps and higher. Such devices are differentiated from a source-synchronous interface in that the receiver device contains a clock data recovery (CDR) circuit. is dynamically determines the optimal sampling point of the data signal based upon the transi- tion edges of the signal. In other words, clock information is extracted directly from the data stream rather than relying on a separate clock. Also, signal integrity concerns frequently dic- tate that the data signal be equalized at the transmitter and/or receiver to counter the effects of the transmission channel and decode the signal properly. Ten-bit transmission code was developed by IBM in the early 1980s. Called the 8b/10b code, the serializer maps each parallel data byte to a 10-bit code onto a serial pair. is code guaran- tees both multiple edge transitions every cycle as well as DC balance. It also provides a way to check for errors and send control informa- tion. Frequent edge transitions in the stream allow the receiver to synchronize the incoming data. DC balance facilitates driving AC-cou- pled loads, long cables, and optical modules. 8b/10b SERDES coding is well suited to serial- izing data such as cell or packet traffic across backplanes, cable, and fiber. Many standards such as ethernet, fiber channel, etc., use the popular 8b/10b coding at high data rates. Implementing high-speed serial links can be challenging for the PCB designer. Any small discontinuity in the physical geometry along the transmission path can significantly degrade the signal. is degradation includes loss of amplitude, reduction of rise time, and increased jitter. As a result, one must be able to identify these discontinuities in the high-speed channel and mitigate their impact to improve the performance of the signal transmission. A capacitor is typically placed in series with both differential signals to remove common mode voltage differences between ICs or dif- ferent technologies. An "AC coupling capaci- tor" or "DC blocking capacitor" basically refers to the same thing. Any capacitor placed in series with the signal path tends to pass the high-frequency AC portions of the signal, while simultaneously blocking the low-frequency DC portions. ese capacitors are essential to a variety of high-speed interfaces. And, as the next generation of designs target data rates of 56 Gbps and above, it becomes increasingly important to characterize channel transitions accurately to ensure a high confidence of suc- cess. As such, PCB designers need to take par- ticular care routing serial interconnects. It is always best to route critical signals on internal stripline layers. However, since the AC coupling capacitors are placed on the outer microstrip layer, routing on the outer lay- ers becomes necessary to avoid discontinui- ties, layer transitions, and via stubs that create

Articles in this issue

Archives of this issue

view archives of Design007 Magazine - Design007-June2021