Design007 Magazine

Design007-Sep2021

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SEPTEMBER 2021 I DESIGN007 MAGAZINE 65 new design utilizing these new manufacturing capabilities. Designers have a learning curve to navigate. Fabricators have a learning curve to navigate. Collaborating with and supporting both as the industry adopts these new tech- nologies is sure to shorten the learning curve for all. DESIGN007 Tara Dunn is the vice president of marketing and business development for Averatek. To read past columns or contact Dunn, click here. routing was still accomplished in those four layers. Because we were having a detailed dia- logue through this process, it was also sug- gested that reducing this design from eight layers to six layers, adding in additional power and ground layers, would still result in a sim- plified construction while at the same time potentially yielding power benefits that had previously not been available. Interesting to ponder, isn't it? One certainty I can bring to this discussion is that semi-additive processes can significantly simplify complex designs. Some are working to simplify existing designs; others can create a The exponential growth in data center infrastructure for IT network- ing introduced numerous challenges, from limited ecosystems to high-per- formance computing issues. There are many constraints on building data centers and updating the equipment in them. Planning is critical in manag- ing increased capacity in the existing data center space. Increased rack density disturbs the prevailing power distribution infrastructure. When more devices are added to the existing space, temperature increases, and the need for containment solutions and precision cooling arises. Also, the components must be able to handle higher temper- atures. Managing load capacity/phase power and weight of the equipment is another challenge. In addition, racks also have energy efficiency issues, and rack depth can cause incompatibility with newer designs. While other challenges in the context of hardware and software exist—like advanced node implementation at 7nm and verification of complex domain-specific architectures—this section focuses mainly on system analysis aspects. Data centers require high-computing devices in small footprints. With a decrease in transistor size, an advanced node is created. Small form factor brings several gains like higher den- sity and faster switching. However, at the same time, advanced nodes take the design and integration complex- ity to a new level. Decreasing metal pitch leads to coupling effects and signal integ- rity issues. Increasing wire and via resistance requires more advanced and variable wire sizing and tapering techniques to compensate. Server signals, chip complexity and cost, power management and electro- migration, achieving performance goals, lithography limitations, pro- cess complexity and variability in extraction, tim- ing, signal integrity analysis, and modeling, pack- age complexity, shorter time-to-market, and project management (engineers/project cost) are some of the critical challenges in advanced node chip design. To download this free eBook, published by I-Connect007, click here. To view the entire I-Connect007 eBook library, click here. Excerpt: The System Designer's Guide to… System Analysis Chapter 2: Challenges in Design and Development of Electronic Systems

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