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38 DESIGN007 MAGAZINE I APRIL 2022 What about power and ground layers? Do all layers need to be produced with these ultra-high density feature sizes? It is most common to use a hybrid approach utilizing both subtractive etch layers and SAP layers in the same printed circuit board stackup. Stackups do not need to be all semi-additive or all subtractive. e layers do not need to be either one technology or the other. Typically, signal layers will utilize SAP technology, oen to simplify the breakout of ever smaller BGA packages, reducing the number of layers and the number of lamination cycles required for the design. Traditional subtractive etch tech- nology can then be used for layers that contain only larger feature sizes. Can SAP processes also produce larger feature sizes? Does the entire layer need to have the same trace and space dimension? SAP processes can produce larger feature sizes as well. In fact, there are signal integrity benefits to these semi-additive processes that make this fabrication technique sought aer, independent of the ultra-high density routing benefits. Just a quick peek into the fabrication pro- cess: e SAP processes move the limiting fac- tor for fabrication from the etching process to the photolithography process. Independent of the seed layer of copper selected, which may be a thin copper foil (mSAP), or an ultra-thin layer of electroless copper (SAP), the dry film resist is patterned, and electrolytic copper is then used to form the printed circuit board traces that were patterned. e lower limits of those trace capabilities and the tolerance of the circuit traces formed vary based on the process used. e mSAP processes, even with an ultra-thin copper foil, have a seed copper layer that is considerably thicker than the electroless copper seed layer used in the A-SAP process. Because the seed layer of copper needs to be etched where it is not required, the thicker copper will take lon- ger to etch, which impacts the trace itself. Both the line width and space need to be larger with the mSAP process and the line width tolerance will need to be greater than with the A-SAP process. While both processes provide an improved line width tolerance, the A-SAP pro- cess with thinner electroless leaves the circuit sidewalls straight with no trapezoidal effect. Tip: Adjust your modeling soware to show traces with no trapezoidal effect and investi- gate how this changes the numbers. In fact, this should be a topic for a future column. Can outer layers and plated through-holes be created with SAP processes? Yes, a PCB designer can confidently design a printed circuit board with ultra-HDI fea- tures on outer layers and connect with reliable plated through-holes using the A-SAP pro- cess. When working with mSAP, circuitry on the outer layers is most oen discouraged. Fabricators building with A-SAP have been running regular lots of material using standard D-coupons with stacked and staggered micro- vias to help PCB designers and OEMs feel comfortable with the reliability of the plated through-holes created with the electroless seed layer of copper I've explained. What is the minimum spacing from trace to pad (external layer)? e copper-to-copper spacing can be a cost adder in subtractive etch processes. In the It is most common to use a hybrid approach utilizing both subtractive etch layers and SAP layers in the same printed circuit board stackup.