Issue link: https://iconnect007.uberflip.com/i/1464168
APRIL 2022 I DESIGN007 MAGAZINE 75 possible for the test program engineer to cre- ate the test patterns used to accomplish the test. is data allows the system to detect and isolate any faults for all boundary-scan testable nets within the circuit. It is also possible for the test program developer to create test vectors that enable the system to detect faults on the nodes or pins for non-boundary scan components that are surrounded by boundary scan devices. While requirements may vary, most docu- ments required for setting up assembly test are quite standard to the industry. ese include: • Assembly detail: is will include graph- ics representing component outline, loca- tion, and reference designators for each device mounted on the board surface • Electrical schematic diagram: Will fur- nish interconnect detail between all pas- sive and active components mounted on the board's surface with corresponding reference designators • Circuit board fabrication detail: Will include the primary mechanical outline dimensions, tooling locations, materials specified for fabrication, and circuit layer sequence with a representative cross- section detail • CAD file: e digital data developed for component placement and circuit inter- connect will furnish specific X-Y compo- nent coordinates, component orientation, and features provided for test probe access • Gerber file: e Gerber file is a standard vehicle developed for PCB design data storage or transfer of PCB circuit image for each layer of the board and includes solder mask and nomenclature images • Bill of materials: All components are listed by type, value and/or identifying part number and quantity. For two sided SMT assembly, component types are to be separated and identified by where located • Approved vendor list: e vendor list represents the user's "qualified suppliers" for all materials and components desig- nated for the circuit board assembly • Netlist: Identifies the electrical connec- tions (node) between component termi- nals in the circuit. e list will include component reference designators, compo- nent type, and terminal numbers • Test node X-Y coordinates: e specific location of each node identified on the netlist must be referenced from a single fiducial target feature chemically etched within the circuit pattern In addition to the documentation noted above, the circuit board developer will fur- nish requirements related to the end product's expected operation or use environment and include key data for all non-standard semicon- ductors. Boundary Scan Test Compliance Prior to releasing the board for fabrica- tion, the designer and/or cognizant engineer responsible for developing the board will review the design with the test program devel- oper to ensure the end-product can be tested effectively. If the design cannot meet full probe access to all nets or boundary scan terminals, the test fixture developer will probably request the addition of any test lands needed to enable the effective probing of all nodes in the net- work. Doing so may challenge the designer in altering the design to add test probe features, but the change will not likely affect the price of the actual circuit board fabrication. However, it will make a significant difference in achieving 100% testability of the PCB design. DESIGN007 Resources 1. JTAG Technologies, Technical support Ameri- cas: support@jtag.com. 2. XJTAG Technologies, "Design for Test Guide- lines:" enquiries@xjtag.com. Vern Solberg is an independent technical consultant, specializing in SMT and microelectronics design and manufacturing tech- nology. To read past columns or contact Solberg, click here.