Issue link: https://iconnect007.uberflip.com/i/1481876
66 PCB007 MAGAZINE I OCTOBER 2022 adhesion of the photoresist to the copper sur- face. Also, fabricators are asked to use lower- profile copper for signal integrity. ese impact adhesion of the resist. To ensure that the image of the circuitry conforms as close to the desired design as possible (i.e., lines and spaces), surface preparation of the copper foil sur face i s o n e o f t h e m o s t c r it ical s ucce s s fac- tors. Employing the optimum mix of sur- face cleaners, micro- etchants, and surface topography modifiers will provide a clean v irgin sur face free o f s o i l s , c o n v e r - s i o n c o a t i ng s , a n d organics, as well as impart a microrough- ened surface to further enhance the adhesion of the resist. The Surface of Copper As previously discussed, as clean as the incoming copper-clad laminate and copper foil appear, there is more work to be done prior Introduction e photolithography process defines the circuitry on the panel. As one may surmise, the imaging process used in the fabrication of high-density and ultra high-density cir- cuitry has made significant advances over the l a s t d e c a d e — a n d just in time, as cus- tomers demand finer lines and spaces, as well as more atten- t ion to fabr icat ing advanced packaging substrates. However, as is so true of many of the processes in P W B f a b r i c a t i o n , upstream and down- stream processes can and w i l l inf luence what happens in a par ticular process. As an example, one can encounter voids in the via. It would be easy to assign root cause to the electroless copper process. Yet, a void in the via can originate due to debris le in the via, smooth resin surface due to less than opti- mum desmear, or aggressive micro-etching in the electrolytic copper plating as well. One can see that surface preparation plays a role in the Success in Photolithography Starts With Surface Preparation Trouble in Your Tank by Michael Carano, AVERATEK