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March 2014 • The PCB Design Magazine 65 and air. The two extremes are the blue and red traces: blue refers to the poorly shielded cable, and the red trace shows the transmission with a quality cable, both with open ends. These cor- respond to the information in these two cases in Reference 1. The red trace is hardly above the noise floor of the instrument; the blue trace has multiple big peaks. The sharp 40MHz peak is related to the quarter-wave resonance of the ca- bles, which is one quarter of the inverse of the end-to-end delay. With termination at the far end (green trace) the crosstalk pattern changes, but only ever so slightly: it is somewhat lower in the 40–70 MHz frequency range, but it gets higher above 80 MHz. With the poor quality cable, we can lower the 40MHz peak by put- ting absorbing ferrites around the cable (shown by the grey trace). The 40 MHz peak got lower by about 25 dB, and the higher-frequency reso- nances got also reduced by 5–10 dB. This illustrates that when at least one of the two cables has a quality shield, the coupling path between them is blocked, and the crosstalk drops, regardless of how the far ends are ter- minated. When both the aggressor and victim cables have poor shielding, the crosstalk at the resonance frequencies is significant, though ter- mination and ferrite absorbers can help a little. In an electromagnetic susceptibility scenario, such as the one we described in the column in Reference 1, we focus on the victim and may not even know where the aggressor is or what generates the aggressor signal. In those situa- tions the quality of the cable shield makes a big difference. PCBDESIGN References 1. Quiet Power column, Comparing Cable Shields, December 2013. 2. MiniVNA-Pro available here. Dr. istvan novak is a distin- guished engineer at oracle, working on signal and power integrity designs of mid-range servers and new technology developments. With 25 patents to his name, novak is co-author of "Frequency-Domain Characterization of Power Distribution networks." To read past columns, or to contact novak, click here. ever since the integrated circuit made its debut, semiconductors have been "single-story" affairs. But chipmakers are now considering ways to build additional transistor-packed layers right on top of the first. in a monolithic 3D circuit, a chipmaker would simply continue building on top of a 2D chip, adding an additional layer of silicon on which another set of circuitry could be built. The vertical connections made in this process could potentially be as dense as those found on a 2D logic chip. if such circuits could be made, chip- makers might be able to avoid all the technical complications associated with shrinking circuitry. But the process is less straightforward than it sounds. Temperatures upwards of 1,000°C are typically used to force dopant atoms into silicon and create the semiconductor portions of the transistor. Applying such heat to create a second layer of transistors could destroy cru- cial components in the first, including salicide, a metal-silicon alloy used to help carry signals in and out of devices. When it comes to memory, monolithic 3D fabrication already seems to be making inroads in industry. in August, samsung announced it had begun production on nAnD flash with memory cells arranged along dense vertical lines, and other companies have similar plans. But details are scant on the particulars of the manufacturing process. "Memory looks like it's already commercial - ized. logic has a long way to go," says sung Kyu lim of Georgia Tech. in the future, he says, "the only way to go to add more devices will be vertical." The Rise of the Monolithic 3D Chip quiet power CHECKING CABLE PERFORMANCE WITH VNA continues

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