SMT007 Magazine

SMT-May2014

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50 SMT Magazine • May 2014 Stable and reliable test procedures are im- portant to avoid unnecessary, and sometimes costly, delays in production. When these require some form of test fixture connecting a device under test (DUT) to the automatic test equip- ment (ATE), poor signal integrity between the two can often make tests unreliable. Identifying and resolving such problems can be time con- suming, but by following some simple guide- lines when designing both the DUT and fixture, test stability can be significantly improved. JTAG Test Access Port (TAP) signals, used to implement boundary scan testing, will be used as an example, although other test and pro- gramming protocols can also benefit by follow- ing these guidelines. minimising the Loop area When signals are connected within a test fixture it is quite common for the wires carrying those signals to be given far more consideration than the return ground connection. A ground is likely to be included somewhere, but could it be improved? With low-frequency and DC signals, the routing of ground wires relative to the signal wires can be different without any obvious side effects. However, as the frequency of the sig- nals increases, the routing of the ground wires becomes more and more significant, up to the point where getting matched impedances is im- portant. For TAP signals, such levels of precision are often not necessary; however minimising the loop area is a good rule of thumb. The key to identifying the loop area is to de- termine: 1. The route that a signal's current will take from its source to destination. This is often easy to establish, because it is the same route as the signal's wires and tracks. 2. The route that a signal's associated return (ground) current will take from the destination back to the source. This can be slightly harder to establish, but can be approximated by assum- ing it stays as close to the signal as possible. feATuRe by Rob Humphrey XJTAg Signal Integrity in Test Fixtures

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