Issue link: https://iconnect007.uberflip.com/i/304995
56 SMT Magazine • May 2014 SIGNaL INTEGRITy IN TEST FIXTURES continues feATuRe so that there is one ground core between each TAP signal in the ribbon cable. If the number of available pins is limited, as a minimum try to include ground cores on both sides of clock signals, such as TCK. Even with a well designed test fixture and good test signal connections to the DUT, it is still possible to make JTAG tests unreliable if a PCB is not designed correctly. Leaving the rout- ing of the TAP signals until last might initially appear to be sensible: They're only for testing the board, so why not route all functional sig- nals first? The problem is that this can result in poorly routed signals that can make the testing unreliable, and in the worst case can even re- quire a new board design, resulting in signifi- cant extra expense and delay. It is worth keeping in mind that TAP signals can clock at frequencies exceeding 20 MHz. This means they should be treated just like any other signals at similar frequencies: • Correct signal termination should be ap- plied to the signals, as specified in JTAG DFT guidelines. These follow standard good design practices, such as placing parallel termination resistors as near to the receiver end of a track as possible. • Avoid stubs in tracks, and use buffers to improve signal fan-out. • Route TAP signals over a continuous ground or power plane. If there are breaks in this then the loop area is increased, making the board more susceptible to unreliability during test. Figure 5a demonstrates how the rout- ing of a TAP signal trace (red) across a break in a ground plane can affect the return cur- rent path (black dash). This results in a larger loop area than initially expected, deteriorat- ing the signal integrity. Although the signal track is longer in Figure 5b, the total loop area is still reduced and so this would be the pre- ferred solution if the ground plane could not be changed. Summary Minimising the loop area will always be a rule of thumb, and as such is not always ap- plicable. However, by being more aware of the route a signal's return current will take, this can provide a solid foundation when design- ing PCBs, determining the pin-outs for connec- tors, and designing and building test fixtures. By considering this as part of the design pro- cess, costly and time-consuming delays later in the development cycle can be avoided. Where available, DFT guidelines should also be con- sulted, because these will contain additional in- formation to further improve the testability of DUTs and the reliability of these tests. Figure 5: return current through a ground plane (black, dashed) will follow the signal trace on a different layer (red) where possible. routing over breaks in the ground plane (a) can significantly increase the loop area, and so should be avoided (b).