PCB007 Magazine

PCB-July2014

Issue link: http://iconnect007.uberflip.com/i/340751

Contents of this Issue

Navigation

Page 53 of 92

54 The PCB Magazine • July 2014 todd Kolmodin is the vice president of quality for gardien Services uSa. to contact Kol- modin, click here. Manfred ludwig is director of operations at gardien Services china. howard carpenter is applications specialist at gardien Services uSa. rick Meraw is senior VP at gardien Services uSa. do. Flying probes use what is called adjacency testing for shorts. One reference probe is set on a net and the other probes measure for leakage in adjacent nets. This window is defined during the CAM process. As with the grid test machines the same charge time variable is introduced and can cause false errors to be reported. Earlier software packages driving these machines did not have an accurate way to delay the read- ing and they were not able to provide a pass to the product which required a manual veri- fication of the error and a hu- man decision made to whether the board was good or not. This was the same with the older grid test machines. Some newer software pack- ages for the flying probers did in fact incorporate delay tim- ers to combat the capacitive charge. However these timers were applied to the entire test which would slow the machine down. Although it was a solution it adds time to the overall test on the flying probe. Another known software package for the flying probe in- troduced a bit of AI to the test routine which ac- tually monitors for this charging variable. This allows the machine to run at full speed until it detects a possible short. It then falls into a delay routine and takes multiple measurements of the suspect net to determine if it is a capaci- tive charging variable or an actual short. If the resistance between the two nets charges and a stable resistance reading is obtained within the test parameter threshold the machine will pass the network and move on. If the leakage continues in excess of the timer measurement threshold a true short is indicated and the net will be flagged as a failure. This advantage al- lows the overall test time of the PCB to remain optimal rather than slowing down every mea- surement reading resulting in lost velocity and throughput. Conclusions As technology grows and PCB sizes shrink the demand for embedded technologies will only grow. Many end-users are designing em- bedded passives into their products and the electrical test community is expected to pro- vide the test solutions for these new powerful designs. The use of buried resistors is increas- ing and care must be taken to identify these com ponents during the ET CAM process so that the test machines are aware of them and do not overpower them with standard test parameters. For the design community that uses the bur- ied core technology the manu- facturers of this material have always recommended using the largest configuration for the buried resistor as feasible. As noted previously the square should be as large as feasible to provide the required resis - tance while also maintaining the optimum power dissipa- tion level to ensure long life and stability. Buried capacitance has been around for a long time but is also increasing. The ability for electrical test to accurately test this type of product is crucial. Accurately iden- tifying and allowing the buried capacitance component results in improved throughput and delivery. It also reduces unnecessary delays, troubleshooting and unfortunate scrap of prod- uct that is actually good. PCB If the resistance between the two nets charges and a stable resistance reading is obtained within the test parameter threshold the machine will pass the network and move on. " " ELECTRICAL TESTING OF PASSIvE COMPONENTS continues

Articles in this issue

Links on this page

Archives of this issue

view archives of PCB007 Magazine - PCB-July2014