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74 The PCB Magazine • July 2014 is dictated by the board layout and the Z by the flatness when tested. Note, as test voltage goes up time also is needed to create then dis- charge it increases so test time also increases especially above 250V. Because moving probe testers do not contact all testing points at the same time the motion of the probes to the testing points gov- erns the test time and therefore cost. Isolation testing takes consid- erably more combined moves than continuity testing and therefore is the major consideration in total test time. ADV is a distance that is used in software applications to determine which nets will be tested against each other for isolation. The basic logic is if two nets are never ex- pected to short against each other the test can be eliminated (i.e., two small nets on opposite sides of the board separated by several inches). Net combinations that have a potential to short to each other should be tested. ADV is used to divide the tested from the non-tested net combinations. The first and most basic use of the method simply uses a dis- tance between features to determine the list. If any feature of a net came within the chosen distance from a feature on another net the two were tested against each other for a short. Line of sight added some logic to the pre- vious method by further analyzing the set of tested nets to see if some of the tests could be eliminated. The logic was if two nets were to be tested against each other but the results could be known by analyzing other tests that test could be eliminated. In physical terms, if two nets can't be shorted without shorting to an intermediate net (straight line) then the test is eliminated and the intermediate tests are used to guarantee the test integrity. Line of sight can be a safer test if the adja- cency distance is increased. The total number of tests is not increased by the previous formu- la because the tests have been eliminated that would be detected by other shorts tests. Through-hole spacing is generally greater than surface mount spacing per device but both are commonly on the same board. Many boards have a mix of the two, so the larger value should be chosen. The test takes longer than it would for the sur- face mount features because a smaller ADV would have been chosen if the through-hole de- vices were not on the board. A major advancement in choos- ing the proper adjacency value would be to separate the dis- tances into different categories, such as: through-hole, surface mount, single point nets, user- defined points per net (nets with 10 endpoints or less), trace width (nets with trace width larger than 20 mills). To have a minimum number of tests per net a net must be tested against two other nets. Currently the ADV is cho- sen then the CAM software develops the list of isolation tests and the programmer is made aware of the number of tests. This information can be used to judge the initial value chosen and this can be an iterative process. In practice, the process is rarely repeated. The logical place for a rigorous evaluation is in the test extrac- tion software. Because printed circuit boards are unique, it isn't possible to choose a single adja- cency distance for all boards. There is no simple formula that can cover all possibilities; only through software analysis can the best value can be achieved. Evolving software tools need to be vetted and ongoing feedback to the IPC subcommittee on electrical test is in the best in- terest of all stakeholders. PCB Figure 1: examples of isola- tion test vs. number of nets. rick Kaim is the president of ally Supply inc. to contact the author, click here. ISOLATION TESTING AND ADJACENCY continues