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PCB-Oct2014

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October 2014 • The PCB Magazine 75 DRY FILM PHOTORESIST ADHESION TESTS continues then processed (e.g., through development and etching) and the resist adhesion is judged by the number of smallest dots that survive. Degree of Resist Lifting in Pattern Plating Degree of resist lifting can be measured by inspecting pattern plated boards after copper plating, but before resist stripping, with a high power microscope. The color of the lifted resist is a lighter blue than the darker blue observed in the region where the resist is in close contact with the copper surface. The width of the ob- served color change under the lifted resist can be recorded in microns. One observes that the degree of lifting on a given board varies with the dimension of the resist feature, not the size of the adjacent copper area. Therefore one mea- sures lifting on the edge of a well defined large rectangular resist area. Three measurements from each of six test boards can be averaged. Yield Print & etch yields as determined by AOI can be used to correlate open defect frequency with poor resist adhesion. Defects called out by the AOI are visually inspected, verified, recorded as opens, shorts, space and line width violations, and downloaded to a PC. Yield analysis soft- ware then allows one to eliminate certain types of defects from the calculation that are not of direct interest to the study. For example, "repeat defects" which have to be associated with the imaging step (e.g., phototool flaw, trapped dirt, etc.) are irrelevant to a resist adhesion study and dilute defects pertinent to surface charac- teristics. Likewise, "short" defects in a print & etch study don't speak to poor film adhesion and conformation issues; however, "opens" do. The study in Reference 1 describes yield de- termination in detail, as follows: The test ve- hicle was a single pitch, 75 micron (3 mil) line and space pattern with one-up repeat patterns of nested pair conductors, alternating in direc- tion. The one-ups consist of a 2 x 2 inch (5 x 5 cm) pattern, repeated in an 8 x 10 array which covers a 16 x 20-inch (approx. 40 x 50 cm) to- tal area with 36,000 inches (0.6 miles or 1km) of circuitry. Two test patterns were used, which were mirror images of each other: one for the panel front side and one for the back side. Five boards were processed for each test condition. When a test pattern is used, there arises some difficulty in defining yield. With real boards (at least a one-up real board), it is simple. A real board either has no defects, and is good, or con- tains one or more defects, and is therefore bad. The yield fraction is the number of good boards divided by the total number of boards made. Because a test pattern is not a real board, defining yield becomes more complex. First, the test pattern may contain conductor length equivalent to that of 5–10 real boards. Our test pattern does not contain all of the features pres- ent on a real board, and it contains conductors and spacing finer than most real boards today. The best one can do is to measure the total de- fect count, divide by the total conductor lineage to find defects per unit length, then calculate the average number of defects per panel for a hypothetical real panel by multiplying defects per unit length (from the test vehicle) times the conductor length of the real panel. Finally, one can then estimate a yield from average defects per hypothetical panel. In our case, raw yield data are reported in DEMIs (defects per million inches of circuitry; 1 million inches equal about 16 miles or 25 km). The test pattern has 36,000 inches (0.6 miles or 1 km) of circuitry on each side. The space length is half the length of the lines. For reference, a typical high density 75 micron line & space production panel might have 5,000 inches (125 m) of circuitry. PCB References 1. The Effects of Copper Foil Type and Sur- face Preparation on Fine Line Image Transfer in Primary Imaging of Printed Wiring Boards, B. L. Adams-Melvin, D. R. McGregor, and K. H. Dietz, Proceedings, P.C, World Convention VII, Basel, Switzerland, May 21–24, 1996. Karl dietz is president of Karl dietz Consulting llC. he offers consulting services and tutori- als in the field of circuit board & substrate fabrication technology. to view past columns or to reach dietz, click here. dietz may also be reached by phone at (001) 919-870-6230.

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