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PCBD-Nov2014

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28 The PCB Design Magazine • November 2014 Why so many options? It is because there is not, nor has there ever been, a truly coher- ent approach to the process of selecting pack- age structures for ICs or any other components for that matter. Yes, a roadmap for electronic component lead pitch was introduced with the advent of SMT, and that roadmap said that ev- ery next-generation lead pitch should be 80% of the size of the previous generation lead pitch. The number 80% was arbitrary, but it was held to religiously, even when later it became clear that it made no sense, as will be shown. The original proposal was created for peripher- ally leaded components, for which some sort of planned progression was arguably needed. However, when area array technology became dominant, the rule became an impediment to real opportunity. A simple common grid based on a fundamental pitch was all that was needed. The electronics industry had precedent when the 0.100" grid was the base for all circuit de- sign and assembly. The Nexus of Order and Simplicity If the industry is to find its way back to its roots and simpler times, there is a need for only one base grid pitch to which all components should adhere. The base pitch which seems most practical is 0.5 mm because below that pitch sol- dering gets more difficult and solder-based defects climb. While area array lead format, in the form of land grid array devices, is deemed most ap- propriate for all components, QFN devices can work pro- vided that all of the termina- tions follow the base grid rule. Few leaded components such as discrete resistors, capacitors and tran- sistor can easily be provided with leads which conformed to the 0.5 mm pitch. One advantage of using these bottom termi- nated component formats is that they offer the greatest uniformity in terms of component lead planarity. While soldering may be employed to affix them if one eschews the use of solder and opts to build circuits on top of the components in the manner of Occam/SAFE technology, it also allows the component supplier to bypass the use of solder or a solderable finish: The leads will be plated to directly, using copper and HDI processes as if the leads were internal lands. Eliminating the finish gives rise to the potential to reduce component cost and increase yield because the devices require fewer process steps. As any process or manufacturing engineer will tell you, where there are more process steps to control, the greater the potential for things to go wrong. And they always, it seems, eventually go wrong. In order to achieve this order and simplic- ity, one must first actually believe it is desirable and be willing to make the appropriate chang- es. In the present case the electronic assembly designer must actively weed through, seek out and use components which not only conform to a common base pitch but also most desirably, conform to a common height. The Joint Electronic Device Engineering Council (JEDEC) registers the mechanical out- lines of all of the various com- ponents which component suppliers wish to supply to users. There are literally thou- sands of possible component body options if all permuta- tions are accounted for. JEDEC council members have given letter designations that define component heights with de- sirably low profiles based on established protocol and ac- cepted terminology. These are presently divided into nine different ranges. "Low" com- ponent heights begin at 1.7 mm and extend down to 0.025 mm at the lowest end. Figure 1 illustrates the differences not only between ranges but within individual ranges. Note that in the graphic, the components are all shown with solder ball terminations. The reason for this is that most components used today have such solder ball terminations. One COMPONENT SELECTION FOR EASIER DESIGN & MANuFACTuRE OF ELECTRONICS continues article The leads will be plated to directly, using copper and HDI processes as if the leads were internal lands. Eliminating the finish gives rise to the potential to reduce component cost and increase yield because the devices require fewer process steps. " "

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