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PCBD-Dec2014

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12 The PCB Design Magazine • December 2014 per thicknesses, the fabrication process is not so exact. Each vendor has different equipment and methods. The lamination process shrinks the dielectrics and materials may be changed if not in stock or readily available. The toleranc- es in all areas add up and ultimately a reliable vendor has to make the right combination of adjustments in-process so that when measuring impedance on the test coupon, it fulfills your spec. Trace widths and material thicknesses may change a little, but if the measured imped- ance is within spec then it really doesn't matter what changes were made, as long as the other requirements are not fatally compromised, of course. If the initial stackup is not defined properly, minor acceptable adjustments by the fabrica- tion vendor will not be adequate to fulfill your overall requirements. A wise and experienced vendor will not accept the risk of making major changes to the design data. Dependencies Unfortunately there are many dependen- cies, some of them circular when defining a stackup. The process of determining an effec- tive stackup can be overwhelming. Forgive the next meandering and confusing paragraph, but this is a good example of the difficult process of deciding which variables need to be com- promised or emphasized to reach your goals. It is necessary to reduce the layer count to keep costs down. On some of the largest PCBs, there are well over 10,000 nets, which require many layers for routing. To control crosstalk, you need to increase the spacing between traces which will likely necessitate even more layers. You may also want to run the diff pairs togeth - er through the via array under the BGA, which means the via must be small enough to not only allow the diff pair to run together, but also space the traces far enough apart to attain the desired coupling. These traces also need to be the appropri- ate width in correlation to the thickness of the dielectrics and their material attributes to pro- vide the desired impedance. But if you have too many layers, then the via needs to be bigger otherwise the aspect ratio of hole size to length becomes too great to drill with a good yield. If you make the via hole smaller, you can enable more dense routing but may sacrifice manufac- turing yields. If you make the via hole larger, you may have to split the diff pairs through the BGA fanout via array and negatively im- pact your signal integrity. If you have more lay- ers because you have to split the diff pairs, you will need an even larger via. On top of that, all these factors may require you to develop special fanout patterns in the context of the stackup to support the manufacturing, signal integrity and routing goals. This paragraph touches just a few of the dependencies, yet even so, it describes a daunting task. Where does one start, then? Later, you will see a number of example stackups with their advantages and disadvantages, plus a basic de- scription of which via models and design rules work best. Some signal and power integrity con- cerns will also be addressed. Overview of Stackup Types In the context of boards that have high pin- count BGAs, there are three stackup types of in- terest: 1. Standard Lamination with Through Vias Advantages • Low cost (until layer count becomes too high). • Simple via models. • Simple dielectrics—primarily FR-4. • Mature process. "Everybody does it." • High reliability (until layer count becomes too high). Disadvantages • If layer count becomes too high. • Fewer fabrication vendors can obtain good yields, costs skyrocket. • Can delaminate under high temperatures required for ROHS lead-free soldering. • Via has to be large, reducing route-ability, increasing layers. • Difficult to implement for BGA pin- pitches below 1 mm. • Through-hole vias capacitively couple to every plane layer, and signal losses increase with thickness. HDI LAYER STACkUPS FOR LARGE, DENSE PCBS continues feature

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