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PCBD-Dec2014

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46 The PCB Design Magazine • December 2014 by Barry Olney In-CIrCuIT DesIgn PTy lTD BEYOND DESIGN Signal Integrity, Part 3 column In last month's column, I looked at the ef- fects of crosstalk, timing and skew on signal quality. This month, I will continue to discuss signal integrity, in particular where most de- signers go wrong and how to avoid the com- mon pitfalls. Digital designs become less forgiving as edge rates and frequencies increase. What used to work in the past may not work now, and a different approach to layout may be necessary. Also, there may be many issues that aren't at first apparent, but affect the reliable performance of the product. Signal and power integrity issues, for instance, often manifest themselves as inter- mittent operation, which can be very difficult to nail. So it is best to find these issues during the design process and eliminate them at the source, rather than apply a Band-Aid solution after production. I have analyzed many high-speed boards over the past 15 years and have established a process that I follow in order to achieve effec- tive, consistent results. Not all assessments re- quire expensive analysis tools, but rather com- mon sense. I find that a large percentage of is- sues can be detected just by eye-balling the de- sign—simulators don't pick up everything. The first thing to look at, of course, is the board stackup. The substrate is the most impor- tant component of the assembly and needs to be planned correctly in order to maintain con- sistent impedance across layers, avoid uninten- tional signal coupling and reduce electromag- netic emissions. In Part 1 of this series, I set out the basic rules for stackup planning that should be adhered to. The most important being: All signal layers should be adjacent to, and closely coupled to, an uninterrupted reference plane, Figure 1: substrate with each signal layer adjacent to a reference plane.

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