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48 The PCB Design Magazine • December 2014 creating a clear return path and eliminating broadside crosstalk. Figure 1 illustrates a good stackup in this regard. This brings us to the next issue: split planes and current return paths. With all signal lay- ers turned on in your layout tool, it is diffi- cult to see the wood for the trees. Figure 2 il- lustrates the dense routing of multiple signal layers viewed together (left)—confusing to the sharpest eye—and the bottom layer, with the adjacent plane (right). The best way to simplify this view is to determine which copper plane (either ground or power) that each signal layer is referenced to. Turn on that signal layer and plane layer to view simultaneously. You can then easily see traces crossing split planes. In this case, the thick traces are power so it is of little consequence. But, this could well be di - sastrous if a high-speed signal was to cross the split. This not only presents a signal integrity issue, but will generate extreme amounts of common-mode currents, which typically flow out I/O cables and cause electromagnetic com- pliancy failure. If digital signals must cross a split, in the power reference plane, a quick fix is to place one or two plane decoupling capacitors (100 nF) close to the offending signals. This pro- vides a path for the return current between the two supplies (e.g., 3.3 V —||— 1.5 V). Al- ternatively, if GND planes are used for the cur- rent return, then GND stitching vias should be placed close to each layer transition (via) to create a clear path for the return current. Fortunately, most high-speed designs have nu- merous decoupling capacitors that can usually provide the return path, without the addition of stitching vias. Crosstalk can be coupled trace-to-trace, on the same layer, or can be broadside coupled by traces on adjacent layers. The coupling is three-dimensional. Traces routed in parallel and broadside cause greater amounts of cross- talk than those routed side by side. This is due to the width of the trace being much larger that the thickness, so more coupling occurs in the broadside configuration. Figure 3 shows how the coupling is increased in the broadside con- figuration (top). You can see the electric fields coupling between the traces and planes. Also, these days many stackups use buildup microstrip layers top and bottom of the board. This can be very dangerous as one needs to take particular care of crosstalk caused by traces routed on the adjacent layers. In Figure 4, the red lands are on the top layer and the yellow signal trace in one layer 2. The yellow trace goes directly beneath the top land and the high-speed signal is coupled to the land due to the extremely close proximity (3.4 mil) beyond design SIGNAL INTEGRITY, PART 3 continues Figure 2: Multiple signal layers (left), bottom layer and adjacent plane (right).

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