Design007 Magazine

PCBD-Dec2014

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December 2014 • The PCB Design Magazine 51 Placing series terminators from the begin- ning will not hurt, as they can always be re- placed by zero ohm resistors if not needed—not a great expense, but this can alleviate ringing problems. Terminators do however slow down the signal rise time. If this noise is not constrained, at the source, then it will be coupled into nearby victim trac- es (crosstalk) and radiate to create more EMI. Apart from the issues of EMI, signal integrity and crosstalk, this noise can cause intermittent operation of the product due to timing glitch- es and interference, dramatically reducing the products reliability. Points to Remember: • Digital designs become less forgiving as edge rates and frequencies increase. • Signal and power integrity issues, for in- stance, often manifest themselves as inter- mittent operation. • The first thing to look at is the board stack- up. All signal layers should be adjacent to and closely coupled to an uninterrupted reference plane, creating a clear return path and eliminating broadside crosstalk. Figure 1 illustrates a good stackup in this regard. • The best way to simplify a complex view is to determine which copper plane (either ground or power) each signal layer is ref- erenced to. Then turn on that signal layer and plane layer to view alongside. • If digital signals must cross a split in the power reference plane, decoupling capaci- tors can be placed close to the offending signals to provide a path for the return cur- rent between the two supplies. • If GND planes are used for the current re- turn, then GND stitching vias should be placed close to each layer transition. • Crosstalk can be coupled trace-to-trace, on the same layer, or can be broadside cou- pled by traces on adjacent layers. • Traces routed in parallel and broadside cause greater amounts of crosstalk than those routed side by side. • Buildup microstrip layers can be very dan- gerous, as one must take particular care of crosstalk caused by traces routed on the adjacent layers. • Keep parallel trace segments as short as possible to reduce coupling crosstalk. • Always route the clock to the longest de- lay of the group of signals. This allows the data to settle before it is read by the clock. • Flight time varies depending on the dielec- tric material that the signal propagates in. • If you must use matched length, tighten the tolerance as this will still reduce the skew. • Routing critical signals between the planes can reduce emissions by 10dB or more. • Embedding signals between the planes, also reduces susceptibility to radiation, as well as providing ESD protection. • To avoid noise on waveforms, reduce the driver strength to the medium cur- rent, check for crosstalk, particularly on long segments, or add series terminators. PCBDESIGN References 1. Barry Olney: Beyond Design: Practical Sig- nal Integrity; Beyond Design: Pre-Layout Sim- ulation; Intro to Board-Level Simulation and the PCB Design Process; Beyond Design: Im- pedance Matching: Terminations; Beyond De- sign: Matched Length Does Not Always Equal Matched Delay 2. Howard Johnson: High-Speed Signal Propagation 3. The ICD Stackup and PDN Planner are distributed globally by www.altium.com Barry olney is managing direc- tor of In-Circuit Design Pty ltd (ICD), australia. This PCB design service bureau specializes in board-level simulation, and has developed the ICD stackup Plan- ner and ICD PDn Planner software. To read past columns, or to contact olney, click here. SIGNAL INTEGRITY, PART 3 continues beyond design

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