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54 The PCB Design Magazine • December 2014 PART 3: PERFORMANCE continues without pin optimization for routing, it is a very complex routing problem due to the sheer volume of netlines that cross each other (you can see the mess in Figure 1). When manually routing designs like this, trying to find a way to route these netlines so they don't block each other is the most difficult part. When manually routing starting with one BGA, the routes can be escaped from the fanouts to the edge of the component in a fairly orderly manner, adding them one-by-one or us- ing MultiPlow to do a group of them. It is not too difficult to fill up all the channels on each layer with optimal escape routing at the start. The problem occurs when getting to the target component(s). Routing into a BGA with non- optimized netlines presents a significant prob- lem. Now the routes are nicely ordered, but the netlines cross in a manner that can only be de- scribed as a mess. The initial netlines can be routed into the BGA fairly easily, but as more and more are rout- ed, meandering is required to complete them. It isn't long before the meandering traces block other routing and there are no more channels for new traces. I estimate from my experience that about 30% of these routes need to be un- routed and started in a different direction at the beginning to find an open channel all the way to the target pin or via. This re-route of failed route paths is the greatest contributor to slowing down the rout- ing task. Even rerouting from a different direc- tion at the start doesn't necessarily ensure that the route can be completed. It is a difficult and sometimes frustrating task. Often, additional vias are required to complete the routing. Of course, if pin swapping or automatic pin op- timization is allowed and applied, the routing challenge is less daunting; yet this kind of prep- aration for making routing more direct is not always allowed. What does the sketch router do with escape optimization that makes such a difference? When considering the set of netlines to route, the sketch router will simultaneously escape the sketch routing Figure 2: sketch router escape optimization of tangled netlines.

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