Issue link: https://iconnect007.uberflip.com/i/442619
58 The PCB Magazine • January 2015 by Todd Kolmodin garDien serViCes usa Challenges of Electrical Test testing todd Challenges to electrical test are many, but a few come to mind as the most challenging. What do you think they are? Here's what I think: 3. Pitch and density 2. Volume And the #1 most challenging attribute to electrical test: soldermask! In our arena today, we can solve pitch and density with flying probe machines, and vol- ume with our grid testers, but the catalyst that is in the mix is that pesky soldermask! So why do I bring up that necessary process as a prob- lem for electrical test? Electrical test is an absolute science test based on mathematics and absolutes. Front- end systems rasterize the given data to abso- lutes. If the IPC, Gerber, and ODB++ data show the alignment of layers to the mask, it is an ab- solute measurement. There are no easements for registration. The test points are assigned to the product based on the absolute clearance allowed in the "Golden" data supplied in the CAD Reference. But there is a disconnect. To be blatantly accurate, it never happens. The phenomenon of via cap, via fill and zero- height via fill all come in to play to change the whole game regardless of what the OEM de- signed. Tolerances are never considered. This specifically comes in to play when the OEM expects a certain type of test (i.e., IPC Class III) where mid-points are required, but they have also required via cap on only one side of barrels Column