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54 The PCB Design Magazine • March 2015 component needs a certain amount of decoupling associ- ated with it, instead of just putting all the decoupling ca- pacitors on a page at the end, he basically associates his decou- pling capacitors with that component in the schematic. Then when it gets to the point that you're doing actual placement of the decou- pling capacitors you're going to get violations that tell you that you haven't placed the right capacitors within the right radius of this com- ponent. So we're bringing this constraint-driv- en flow to power integrity that's always been there for signal integrity. KD: Excellent. Let's talk about serial interfac- es. Tell us where they've come from and where we're going with them. BG: One of the most interesting things in signal integrity is around the serial interfaces and it also sort of mixes with memory interface design as well, which is a parallel bus. With se- rial interfaces, the way that we typically check compliance on them is by running many sig- nals which we call high-capacity simulation, and by many I mean like millions and tens of millions of bits. We're looking to see how many of those bits actually get transferred cor- rectly. So when you go to the PCI-SIG, the spe- cial-interest group, they have a bit error rate test that they do with hardware. Well we can do the same sort of bit error rate testing with software. Our signal integrity software supports a high-capacity simulation and then lets you look at the eye diagram and just like with PCI- SIG we have that compliance test built into our software. There are a couple of really interesting things about what's happening in this space. One is the most popular serial interface by far, which is PCI express. We've been at PCIe 3.0 for a few years now, and that's an 8 Gb/s interface. Most people here at DesignCon are talking about up to 28 or 56 Gb/s, so 8 is a little bit behind the bleeding edge at this point. But what's going to be happening this year is PCI-SIG is going to approve the 4.0 spec, which is moving it to 16. Still maybe not on the bleeding edge, but doubling the data rate is very significant. One of the cool things we're showing in our booth is if someone who is using 8 Gb/s today wants to see if their same hardware will support a 16 Gb/s data transfer, we can help them check that feasibility. It's really quite interesting because you can see by default the answer is probably no, the eye is going to be closed and you're not going to meet your bit error rate testing. But be- cause these transceivers and receivers have such advanced equalization in them we have what's called algorithmic models that sit on both sides, transmitter and receiver, and this is the same type of stuff we're going to see in devices that come out and support PCIe 4.0. We can turn on a level of equalization and see if when we boost that signal if we can open up that eye and see if it's going to meet those compliance require- ments that are going to be associated with dou- bling the date rate from 8 to 16. That's a pretty interesting thing that's going to be happening in 2015. But one other thing I just wanted to throw in is when we talked about LPDDR4, that data rate is actually going to go up to as high as 4266, so that's going to be working in a similar way that serial links were working about two or three years ago. The same equalization that you needed in serial links a few years ago are going to be needed in memory interfaces this year. We will support that with our algorithmic modeling interface. We can actually show today AMI modeling associated with DDR4 and LPDDR4 as well as, of course, serial links. It's just tremendously interesting and exciting with all this different technology that we get data passed across the ether into the cloud as fast as possible. All this stuff is really exciting, and the fact that we're able to analyze this and help customers get to market right the first time is what we're really excited about at Cadence, and the Allegro technology is provid- ing that link to getting the product done right the first time. KD: Thanks for taking the time to talk with me today, Brad. BG: Thank you, Kelly. PCBDESIGn article CADEnCE'S BRAD GRIFFIn DIGS DEEP InTO DDR continues

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